SRAM

SRAM

Parameter

Name	Description
DW	data width
AW	Address Width

Port

Name	Direction	Width	Description
data_w	Input	DW	Input write data of SRAM
addr_w	Input	AW	Input write-address of SRAM
data_wstrb	Input	(DW+7)/8	Byte mask of Writeing
en_w	Input	1	write enable
data_r	Output	DW	Output read-data from SRAM
addr_r	Input	AW	Input read-address
en_r	Input	1	read enable
CLK	Input	1	Clock drives the SRAM

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SRAM is the basic element of timing logic. The address of reading and writing is separated, which allows reading and writing at the same cycle.