FPGA Implementation

FPGA Implementation

Program Compile

The Program begins at _prog_start in startup.S, and call main at the end of startup. Make sure register sp has been set up, or the C function call cannot return.

Program Download

The current version has no debugger module, so the elf file needs to be downloaded manually. In FPGA hardware implementation, a JTAG to AXI Master, setting in AXI Full, 64bits address width, 64bits data width, is required to write the program into the SRAM. createDownload.py integrated into the compile.bat can generate download script download.tcl. After FPGA is programmed, use source ./download.tcl in Tcl Console to program the SRAM. Finally, push the reset button to reset the pc register of CPU to 0x8000_0000. By the way, only power-down can reset and clear the SRAM.