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Bypass FIFO
| Name | Description |
|---|---|
| DW | data width |
| Name | Direction | Width | Description |
|---|---|---|---|
| valid_i | Input | 1 | push from pervious stage |
| data_i | Input | DW | Input data from pervious stage |
| ready_i | Output | 1 | Indicate that the bypass FIFO is allowing input at the time |
| valid_o | Output | 1 | Indicate that the bypass FIFO is allowing output at the time |
| data_o | Output | DW | Output data to next stage |
| ready_o | Input | 1 | Allow the bypass FIFO to output the data |
| flush | Input | 1 | Synchronous reset of Bypass FIFO. Active High |
| CLK | Input | 1 | Clock drives the Bypass FIFO |
| RSTn | Input | 1 | Asynchronous reset of Bypass FIFO. Active Low |
Bypass FIFO is used to temporally store data between combination logic. The data will be stored in the buff/FIFO when the data comes but the next stage is not ready.
