Skip to content

[AP][Solver] Per-Connection Timing Optimization #3155

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from

Conversation

AlexandreSinger
Copy link
Contributor

The B2B solver originally used a simple net weighting model to incorperate timing into the objective. This works well, but a more direct approach to timing should provide a better solution.

Added extra edges to the B2B formulation which encode per-connection delays into the objective.

Simply, these edges incentivice the solver to shrink the distance between driver and sinks where shrinking that distance would improve the delay the most (focusing more on currently critical edges).

To encode this objective, I compute the instantaneuous derivative of the delay of an connection with respect to the distance (normalized such that the units are not in seconds) and use that as a weight for a pin to pin connection between each driver and its sinks.

More tuning is likely need to find good factors for each term. For now this was what worked well on the VTR benchmarks.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Jun 20, 2025
The B2B solver originally used a simple net weighting model to
incorperate timing into the objective. This works well, but a more
direct approach to timing should provide a better solution.

Added extra edges to the B2B formulation which encode per-connection
delays into the objective.

Simply, these edges incentivice the solver to shrink the distance
between driver and sinks where shrinking that distance would improve the
delay the most (focusing more on currently critical edges).

To encode this objective, I compute the instantaneuous derivative of the
delay of an connection with respect to the distance (normalized such
that the units are not in seconds) and use that as a weight for a pin to
pin connection between each driver and its sinks.
@AlexandreSinger AlexandreSinger force-pushed the feature-ap-per-edge-delay-opt branch from 721159e to b1485d2 Compare June 20, 2025 01:50
@AlexandreSinger
Copy link
Contributor Author

Result on Titan, timing driven with no fixed blocks:

Metric Value normalized to AP baseline
post_fl_hpwl 1.04
post_dp_hpwl 1.00
total_wirelength 1.00
post_gp_cpd 1.01
post_fl_cpd 1.02
post_dp_cpd 0.98
crit_path_delay 0.98

Wintermute was loaded yesterday, so I do not really trust the runtime results; but locally, I have found that GP runtime increased by around 10-20%.

These results match what I have been seeing on VTR. The post-GP and post-FL results appear to get a bit worse; however overall the result gets better. I believe what is causing this behavior is that the timing analysis and wirelength analysis I am performing during GP is so early that it is more of a guide than truth. Since my timing objective that I added is focused more on the router lookahead than the criticalities that I compute, it appears to do worse in GP but actually does better overall.

Much more tuning is needed. but I think this is good enough to replace the net weighting approach for now. I want to continue to tune and prod this over time.

@AlexandreSinger
Copy link
Contributor Author

@vaughnbetz This is the code for the timing slides I presented to you on Monday. I was able to focus the objective entirely on the derivative formulation for timing. After my recent updates to the solver, that objective formulation began winning out. Still lots of noise, but I agree with you that its very intuitive.

@amin1377 FYI. Your review would also be appreciated. Also I think you will find this interesting.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
lang-cpp C/C++ code VPR VPR FPGA Placement & Routing Tool
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant