verilog-to-routing · Tulong4Dev · Jun 17, 2022 · Jul 26, 2022 · Jul 26, 2022 · Jul 28, 2022
diff --git a/CMakeLists.txt b/CMakeLists.txt
@@ -31,6 +31,7 @@ option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers (
 option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF)
 option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF)
 option(VTR_ENABLE_DEBUG_LOGGING "Enable debug logging" OFF)
+option(VTR_ENABLE_VERSION "Enable version number up-to-date during compilation" ON) 
 option(VTR_ENABLE_VERBOSE "Enable increased debug verbosity" OFF)
 option(SPEC_CPU "Enable SPEC CPU v8 support" OFF)
 

diff --git a/doc/src/vpr/command_line_usage.rst b/doc/src/vpr/command_line_usage.rst
@@ -358,13 +358,13 @@ Use the options below to override this default naming behaviour.
 
     .. seealso:: :ref:`Routing Resource XML File <vpr_route_resource_file>`.
 
-.. option:: --read_vpr_constraints <file>
+.. option:: --read_vpr_constraints <file1>:<file2>:...:<fileN>
 
-    Reads the :ref:`floorplanning constraints <vpr_constraints_file>` that packing and placement must respect from the specified XML file.
+    Reads the :ref:`floorplanning constraints <vpr_constraints_file>` that packing and placement must respect from the specified XML file; and/or reads the :ref:`global route constraints <vpr_constraints_file>` that router must respect from the specified XML file. Multiple files are allowed and should be seperated with a colomn char. 
 
 .. option:: --write_vpr_constraints <file>
 
-    Writes out new :ref:`floorplanning constraints <vpr_constraints_file>` based on current placement to the specified XML file.
+    Writes out new :ref:`floorplanning constraints <vpr_constraints_file>` based on current placement to the specified XML file; and/or writes out new :ref:`global route constraints <vpr_constraints_file>` based on current global routecounstraints to the specified XML file. Note that a single combined file is written to even there are multiple input constraint files read in.
 
 .. option:: --read_router_lookahead <file>
 

diff --git a/doc/src/vpr/route_constraints.rst b/doc/src/vpr/route_constraints.rst
@@ -0,0 +1,44 @@
+
+VPR Route Constraints
+=========================
+.. _vpr_constraints_file:
+VPR supports running flows with route constraints. Route constraints are set on global signals to specify if they should be routed or not. For example, a user may want to route a specific internal clock even clock modeling option is set to not route it.
+
+.. note:: The constraint specified in this file overrides the setting of option "--clock_modeling" if it is specified. A message will be issued in such case: "Route constraint(s) detected and will override clock modeling setting". 
+
+The route constraints should be specified by the user using an XML constraints file format, as described in the section below. 
+
+A Constraints File Example
+--------------------------
+
+.. code-block:: xml
+	:caption: An example of a route constraints file in XML format.
+	:linenos:
+
+	<vpr_constraints tool_name="vpr">
+                <global_route_constraints>
+                        <!-- specify route method for a global pin that needs to be connected globally -->
+                        <set_global_signal name="(int_clk)(.*)" type="clock" route_model="route"/>
+                        <set_global_signal name="clk_ni" type="clock" route_model="ideal"/>
+                        <set_global_signal name="rst" type="reset" route_model="ideal"/>
+                </global_route_constraints>
+	</vpr_constraints>
+
+.. _end:
+
+.. note:: The "route_model" in constraint specified in this file only support "ideal" and "route" only.
+
+Constraints File Format
+-----------------------
+
+VPR has a specific XML format which must be used when creating a route constraints file. The purpose of this constraints file is to specify 
+
+#. The signals that should be constrained for routing
+#. The route model for such signals 
+
+The file is passed as an input to VPR when running with route constraints. When the file is read in, its information is used to guide VPR route or not route such signals.
+
+.. note:: Use the VPR option :vpr:option:`--read_vpr_constraints` to specify the VPR route constraints file that is to be loaded. 
+
+.. note:: Wildcard names of signals are supported to specify a list of signals. The wildcard expression should follow the C/C++ regexpr rule.
+
diff --git a/libs/EXTERNAL/libcatch2/src/catch2/internal/catch_fatal_condition_handler.cpp b/libs/EXTERNAL/libcatch2/src/catch2/internal/catch_fatal_condition_handler.cpp
@@ -202,7 +202,7 @@ namespace Catch {
     FatalConditionHandler::FatalConditionHandler() {
         assert(!altStackMem && "Cannot initialize POSIX signal handler when one already exists");
         if (altStackSize == 0) {
-            altStackSize = std::max(static_cast<size_t>(SIGSTKSZ), minStackSizeForErrors);
+            altStackSize = std::max(static_cast<size_t>(/*SIGSTKSZ*/32768), minStackSizeForErrors);
         }
         altStackMem = new char[altStackSize]();
     }

diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h
@@ -166,8 +166,11 @@ enum e_pin_type {
 enum e_interconnect {
     COMPLETE_INTERC = 1,
     DIRECT_INTERC = 2,
-    MUX_INTERC = 3
+    MUX_INTERC = 3,
+    NUM_INTERC_TYPES /* Invalid type */
 };
+/* String version of interconnect types. Use for debugging messages */
+constexpr std::array<const char*, NUM_INTERC_TYPES> INTERCONNECT_TYPE_STRING = {{"unknown", "complete", "direct", "mux"}};
 
 /* Orientations. */
 enum e_side : unsigned char {
@@ -1468,7 +1471,7 @@ enum e_directionality {
     BI_DIRECTIONAL
 };
 /* X_AXIS: Data that describes an x-directed wire segment (CHANX)                     *
- * Y_AXIS: Data that describes an y-directed wire segment (CHANY)                     *     
+ * Y_AXIS: Data that describes an y-directed wire segment (CHANY)                     *
  * BOTH_AXIS: Data that can be applied to both x-directed and y-directed wire segment */
 enum e_parallel_axis {
     X_AXIS,
@@ -1513,7 +1516,7 @@ enum e_Fc_type {
  * Cmetal: Capacitance of a routing track, per unit logic block length.      *
  * Rmetal: Resistance of a routing track, per unit logic block length.       *
  * (UDSD by AY) drivers: How do signals driving a routing track connect to   *
- *                       the track?  
+ *                       the track?
  * seg_index: The index of the segment as stored in the appropriate Segs list*
  *            Upon loading the architecture, we use this field to keep track *
  *            the segment's index in the unified segment_inf vector. This is *
@@ -1569,12 +1572,12 @@ constexpr std::array<const char*, size_t(SwitchType::NUM_SWITCH_TYPES)> SWITCH_T
 
 /* Constant/Reserved names for switches in architecture XML
  * Delayless switch:
- *   The zero-delay switch created by VPR internally 
+ *   The zero-delay switch created by VPR internally
  *   This is a special switch just to ease CAD algorithms
  *   It is mainly used in
- *     - the edges between SOURCE and SINK nodes in routing resource graphs  
+ *     - the edges between SOURCE and SINK nodes in routing resource graphs
  *     - the edges in CLB-to-CLB connections (defined by <directlist> in arch XML)
- *   
+ *
  */
 constexpr const char* VPR_DELAYLESS_SWITCH_NAME = "__vpr_delayless_switch__";
 
@@ -1910,12 +1913,18 @@ struct t_arch {
 
     char* architecture_id; //Secure hash digest of the architecture file to uniquely identify this architecture
 
+    /* Xifan Tang: options for tileable routing architectures */
+    bool tileable;
+    bool through_channel;
+
     t_chan_width_dist Chans;
     enum e_switch_block_type SBType;
+    enum e_switch_block_type SBSubType;
     std::vector<t_switchblock_inf> switchblocks;
     float R_minW_nmos;
     float R_minW_pmos;
     int Fs;
+    int subFs;
     float grid_logic_tile_area;
     std::vector<t_segment_inf> Segments;
     t_arch_switch_inf* Switches = nullptr;