Support route constraint. #2233

Tulong4Dev · 2023-01-26T22:35:13Z

Description

Allow router to route or skip specific signals.

Related Issue

Currently, VPR ignores or routes a global signal through clock modeling options; it does not allow a specific signal to be treated seperately as desired. See details in Flexible support for clock signal routing #2235

Motivation and Context

Allow route constraints applied to specific signals.

How Has This Been Tested?

Types of changes

Bug fix (change which fixes an issue)
New feature (change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

My change requires a change to the documentation
I have updated the documentation accordingly
I have added tests to cover my changes
All new and existing tests passed

…ting/vtr-verilog-to-routing into tileable_rr_graph

…compileable.

…ting/vtr-verilog-to-routing into tileable_rr_graph

…der file

…nel nodes

tangxifan · 2023-03-17T05:06:22Z

golden_results.txt

This is what I got through my local run. I think you turned on the VTR_ASSERT_LEVEL=3 which may cause the issues.

tangxifan · 2023-03-17T05:08:23Z

I think the santizer option is also on. It causes the issue.

tangxifan

@Tulong4Dev Thanks for the contribution. Code changes look good in general. Need some tuning. Open to discussion.

doc/src/vpr/route_constraints.rst

vpr/src/base/vpr_constraints.cpp

vpr/src/util/vpr_utils.cpp

vpr/src/base/vpr_constraints.cpp

vpr/src/base/route_constraint.cpp

tangxifan

Sorry. Wrong review conclusion.

vaughnbetz · 2023-03-23T17:44:47Z

vpr/src/base/route_constraint.h

+
+/**
+ * @file
+ * @brief This file defines the RouteConstraint class.


I think we should have a bigger comment on what this class is for, what it can currently do, what kind of code belongs here (so people know in the future if there is some new feature code that would best be put here), etc.

vaughnbetz · 2023-03-23T17:45:39Z

@duck2 : can you take a look at the xml parser part of this pull request and give any feedback you think is appropriate? It is building on some of your code.

…-routing into openfpga

… conflict

tangxifan · 2023-04-20T09:35:00Z

@Tulong4Dev I believe you are merging the codes in openfpga branch to the master in this PR. Please do not do so. You can see the code changes now contains 9k lines. A way to clean up is to create a new branch on your fork which only contains the routing constraint -related code changes.

vaughnbetz · 2023-08-02T16:06:46Z

@kimiatkh is hoping this one can be merged soon, as she'd like to build some functionality on top of it. @Tulong4Dev : any ETA? If you're around for the VTR meeting this Thursday at 1:30 pm EST, this could be a good topic to discuss if there is some interaction with you and kimia that could help land this.

Yitian4Debug and others added 30 commits June 16, 2022 19:12

WIP: Allow source node query in rr graph view.

b7cba40

Add tileable rr graph support.

4a05cad

Fix format issue.

619caea

Enable tileable rr graph builder for unidir graph arch; code cleanup.

b749ce1

Fix typo.

3932e1d

Merge branch 'tileable_rr_graph' of https://github.com/verilog-to-rou…

fda9057

…ting/vtr-verilog-to-routing into tileable_rr_graph

Add missing tileable rr graph functions and support class to make it …

aecd504

…compileable.

Code cleanup: fix warnings and format code by complying to vtr format.

17626dd

Code cleanup: change comments format by complying to vtr clang format.

f3a6875

Merge branch 'tileable_rr_graph' of https://github.com/verilog-to-rou…

7b5c8ab

…ting/vtr-verilog-to-routing into tileable_rr_graph

Merge branch 'master' into tileable_rr_graph

c957a44

[vpr] add missing files

3f4a404

[vpr] add the declaration of common rr_graph building function to hea…

6e21663

…der file

[vpr] cleaning up compilation errors

ac554b1

[vpr] adapting API in tileable rr_graph builder

7490a21

[vpr] adapting apis in tileable rr_graph builder

e4fa747

[vpr] enrich error message in rr_gsb

1101588

[vpr] integrating edge builder to rrgraph builder

2bbb7f2

[vpr] syntax error

4d46b47

[vpr] rename header file

3ecee3e

[vpr] add api for node_in_edges

2b71a2c

[vpr] added APIs for node_in_edges and adapt tileable rr graph generator

bef7983

[vpr] add missing API find_edges() for tileable rr_graph builder

38a8569

[vpr] using updated api in tileable rrgraph builder when finding chan…

0af1634

…nel nodes

[vpr] now enable build edges and incoming edges

aba2572

[vpr] syntax

b06c5ba

[vpr] enable tileable rr_graph in create_rr_graph()

314d22a

[test] add a quick test for tileable rr_graph

4f19f8e

[test] enable new test in strong regression test

0b77856

[lib] enable tileable options in read fpga arch library

8c2bc64

Tulong4Dev added 6 commits March 10, 2023 21:14

fix write constraint; update with simple test.

bcc1881

Update new test golden result.

63b028d

update document.

f3b42d2

update golden results.

0dbd685

update golden result from release build.

71db0a4

update golden.

bd59994

update golden result with deep-cleaned build.

8593cb5

tangxifan approved these changes Mar 21, 2023

View reviewed changes

tangxifan requested changes Mar 21, 2023

View reviewed changes

clean up code based on review comments.

294c49b

vaughnbetz reviewed Mar 23, 2023

View reviewed changes

Tulong4Dev and others added 8 commits March 23, 2023 18:02

support route constraints.

1b95c01

Merge branch 'master' into openfpga

458fa39

[core] resovle mering conflicts which causes compilation failures

4c43c74

Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to…

0b915ba

…-routing into openfpga

[core] code format

6ac416c

[test] comment out testcase 'strong_vpr_constraints' due to a merging…

d70659f

… conflict

add missing new line when writing place constraint

42e48e5

Merge branch 'openfpga' into route_constraint_dev

2dc4652

github-actions bot added build Build system external_libs lang-make CMake/Make code libarchfpga Library for handling FPGA Architecture descriptions libvtrutil labels Apr 20, 2023

support packer constraint.

e0dd3c1

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Support route constraint. #2233

Support route constraint. #2233

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Tulong4Dev commented Jan 26, 2023 •

edited by tangxifan

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tangxifan commented Mar 17, 2023

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vaughnbetz Mar 23, 2023

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vaughnbetz commented Aug 2, 2023

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Support route constraint. #2233

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Support route constraint. #2233

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Tulong4Dev commented Jan 26, 2023 • edited by tangxifan Loading Uh oh! There was an error while loading. Please reload this page.

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Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

Checklist:

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tangxifan commented Mar 17, 2023

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vaughnbetz Mar 23, 2023

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vaughnbetz commented Mar 23, 2023

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Tulong4Dev commented Jan 26, 2023 •

edited by tangxifan

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