Install Intel FPGA 'Quartus Prime' software on remote servers
-
Updated
Feb 14, 2025 - Python
#
quartus-prime
Here are 127 public repositories matching this topic...
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
fsm mips tcl labs verilog alu hse modelsim system-verilog mips-architecture quartus-prime quartus miem terasic-de10-lite terasic verilog-designs ddlm schoolmips dmk-press verilog-book
-
Updated
Sep 15, 2023 - Verilog
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto
-
Updated
Jun 9, 2021 - Verilog
Tutorial de instalação do Quartus Prime no Linux
-
Updated
Oct 16, 2019 - Shell
Trying to get a new skill
digital electronics rtl verilog xilinx vivado altera modelsim testbench xilinx-vivado quartus-prime gowin
-
Updated
Dec 31, 2024 - Verilog
Full tutorial about how to install Quartus Prime software in different systems
-
Updated
Nov 8, 2024
A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
-
Updated
Jul 8, 2021 - Verilog
This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
-
Updated
Jan 8, 2022 - Verilog
FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
-
Updated
Dec 16, 2021 - Verilog
This repository contains numerous projects that were successfully implemented on an Altera Cyclone IV FPGA.
fpga electronics vhdl stm32 embedded-systems modelsim quartus-prime altera-fpga rtl-design-and-verification
-
Updated
Nov 8, 2025 - C
Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller
-
Updated
Oct 30, 2017 - Verilog
A Python-based IP Core Management Infrastructure.
infrastructure database simulation vhdl intel python3 xilinx synthesis altera modelsim questasim xilinx-vivado quartus-prime vhdl-verification ip-core riviera-pro
-
Updated
Apr 29, 2021 - Python
Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
build-automation linux-distribution u-boot quartus-prime cyclone-v sd-card-image intel-fpga arria10 soc-fpgas soc-eds
-
Updated
Jun 4, 2024 - Python
A script to convert the Intel Quartus IDE to dark mode using QDarkStyleSheet with some modifications.
-
Updated
Aug 10, 2024 - PowerShell
-
Updated
Jul 14, 2019 - Verilog
Remote control infrared signal receiver programmed in VHDL for a Terasic DE1-SoC board.
-
Updated
Mar 29, 2022 - VHDL
An 8-bit RISC based processor designed in verilog with x86 instructions.
-
Updated
Sep 6, 2021
This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.
c fpga vhdl verilog modelsim quartus-prime de10-lite fpga-design programmable-logic-design softcore-processor-design
-
Updated
Sep 26, 2024 - Verilog
Improve this page
Add a description, image, and links to the quartus-prime topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the quartus-prime topic, visit your repo's landing page and select "manage topics."