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tharinduSamare/README.md

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  1. Ravinduabey/SERIAL_BUS_project Ravinduabey/SERIAL_BUS_project Public

    SystemVerilog 1 1

  2. RISCV_processor_design RISCV_processor_design Public

    This is a RISC-V 32I processor which also supports the M extension.

    SystemVerilog

  3. Multicore_processor_SystemVerilog_design Multicore_processor_SystemVerilog_design Public

    This is a multicore processor specially designed for matrix multiplication.

    SystemVerilog

  4. entc17fyp6/ROS_system entc17fyp6/ROS_system Public

    Static object detection full system.

    Python

  5. entc17fyp6/camera-ros-connect entc17fyp6/camera-ros-connect Public

    Jupyter Notebook 1

  6. UVM_switch_test UVM_switch_test Public

    This is a UVM test bench for a simple combinational switch, designed for learning purposes.

    SystemVerilog 1 1