Add HMR Unit

.github/workflows/ci.yml

@@ -28,7 +28,7 @@ jobs:
         run: pip install -r requirements.txt
       - name: Check clean make targets
         run: |
-          make -B gen_ODRG gen_TCLS gen_ecc_registers gen_ECC
+          make -B gen_HMR gen_ecc_registers gen_ECC
           git status && test -z "$(git status --porcelain)"
   lint-verilog:
     runs-on: ubuntu-latest
@@ -41,18 +41,11 @@ jobs:
             ./rtl
           exclude_paths: |
             ./test
-            ./rtl/*/*_reg_pkg.sv
-            ./rtl/*/*_reg_top.sv
-            ./rtl/ecc_wrap/ecc_manager_2_reg_pkg.sv
-            ./rtl/ecc_wrap/ecc_manager_2_reg_top.sv
-            ./rtl/ecc_wrap/ecc_manager_8_reg_pkg.sv
-            ./rtl/ecc_wrap/ecc_manager_8_reg_top.sv
+            ./rtl/HMR/regs
+            ./rtl/HMR/regs
             ./rtl/ecc_wrap/ecc_manager_reg_pkg.sv
             ./rtl/ecc_wrap/ecc_manager_reg_top.sv
-            ./rtl/ODRG_unit/odrg_manager_reg_pkg.sv
-            ./rtl/ODRG_unit/odrg_manager_reg_top.sv
-            ./rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv
-            ./rtl/pulpissimo_tcls/tcls_manager_reg_top.sv
+            ./rtl/deprecated
           extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal --waiver_files .github/waiver.verible"
           github_token: ${{ secrets.GITHUB_TOKEN }}
           reviewdog_reporter: github-check

Bender.yml

@@ -14,74 +14,115 @@ sources:
     # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
     # levels 1 and 0, etc. Files within a level are ordered alphabetically.
     # Level 0
-  - rtl/ODRG_unit/odrg_manager_reg_pkg.sv
   - rtl/ecc_wrap/ecc_manager_reg_pkg.sv
-  - rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv
-  - rtl/ODRG_unit/triple_core_barrier.sv
   - rtl/hsiao_ecc/hsiao_ecc_pkg.sv
   - rtl/hsiao_ecc/hsiao_ecc_enc.sv
   - rtl/hsiao_ecc/hsiao_ecc_dec.sv
   - rtl/hsiao_ecc/hsiao_ecc_cor.sv
   - rtl/TMR_voter.sv
   - rtl/TMR_word_voter.sv
     # Level 1
-  - rtl/ODRG_unit/odrg_manager_reg_top.sv
   - rtl/ecc_wrap/ecc_manager_reg_top.sv
-  - rtl/pulpissimo_tcls/tcls_manager_reg_top.sv
   - rtl/ecc_wrap/ecc_scrubber.sv
+  - rtl/TMR_voter_detect.sv
+    # Level 2
+  - rtl/bitwise_TMR_voter.sv
+  - rtl/ecc_wrap/ecc_manager.sv
+  - rtl/ecc_wrap/ecc_sram.sv
+    # Level 3
+
+  - files:
+      - rtl/HMR/hmr_pkg.sv
+      - rtl/HMR/resp_suppress.sv
+      - rtl/HMR/rapid_recovery/rapid_recovery_pkg.sv
+      - rtl/HMR/rapid_recovery/recovery_csr.sv
+      - rtl/HMR/rapid_recovery/recovery_pc.sv
+      - rtl/HMR/rapid_recovery/recovery_rf.sv
+      - rtl/HMR/rapid_recovery/rapid_recovery_unit.sv
+      - rtl/HMR/DMR_checker.sv
+      - rtl/HMR/DMR_CSR_checker.sv
+      # - rtl/HMR/DMR_address_generator.sv
+      # - rtl/HMR/DMR_controller.sv
+      - rtl/HMR/rapid_recovery/hmr_rapid_recovery_ctrl.sv
+      - rtl/HMR/regs/hmr_registers_reg_pkg.sv
+      - rtl/HMR/regs/hmr_core_regs_reg_pkg.sv
+      - rtl/HMR/regs/hmr_dmr_regs_reg_pkg.sv
+      - rtl/HMR/regs/hmr_tmr_regs_reg_pkg.sv
+      - rtl/HMR/regs/hmr_registers_reg_top.sv
+      - rtl/HMR/regs/hmr_core_regs_reg_top.sv
+      - rtl/HMR/regs/hmr_dmr_regs_reg_top.sv
+      - rtl/HMR/hmr_dmr_ctrl.sv
+      - rtl/HMR/regs/hmr_tmr_regs_reg_top.sv
+      - rtl/HMR/hmr_tmr_ctrl.sv
+      - rtl/HMR/hmr_unit.sv
+      - rtl/HMR/hmr_rr_wrapper.sv
 
   - target: any(deprecated, axi_ecc, hci_ecc, pulp_ecc, test)
     files:
-      - rtl/ecc_concat_32_64.sv
-      - rtl/lowrisc_ecc/prim_secded_pkg.sv
-      - rtl/lowrisc_ecc/prim_secded_13_8_cor.sv
-      - rtl/lowrisc_ecc/prim_secded_13_8_dec.sv
-      - rtl/lowrisc_ecc/prim_secded_13_8_enc.sv
-      - rtl/lowrisc_ecc/prim_secded_22_16_cor.sv
-      - rtl/lowrisc_ecc/prim_secded_22_16_dec.sv
-      - rtl/lowrisc_ecc/prim_secded_22_16_enc.sv
-      - rtl/lowrisc_ecc/prim_secded_39_32_cor.sv
-      - rtl/lowrisc_ecc/prim_secded_39_32_dec.sv
-      - rtl/lowrisc_ecc/prim_secded_39_32_enc.sv
-      - rtl/lowrisc_ecc/prim_secded_72_64_cor.sv
-      - rtl/lowrisc_ecc/prim_secded_72_64_dec.sv
-      - rtl/lowrisc_ecc/prim_secded_72_64_enc.sv
+      - rtl/deprecated/ecc_concat_32_64.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_pkg.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_13_8_cor.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_13_8_dec.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_13_8_enc.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_22_16_cor.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_22_16_dec.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_22_16_enc.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_39_32_cor.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_39_32_dec.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_39_32_enc.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_72_64_cor.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_72_64_dec.sv
+      - rtl/deprecated/lowrisc_ecc/prim_secded_72_64_enc.sv
 
-  - target: axi_ecc # custom ECC for PULP AXI IPs, make sure to include interface IPs when adding this target
+  # custom ECC for PULP AXI IPs, make sure to include interface IPs when adding this target
+  - target: axi_ecc
     files:
       - rtl/BUS_enc_dec/AXI_bus_ecc_dec.sv
       - rtl/BUS_enc_dec/AXI_bus_ecc_enc.sv
-  - target: hci_ecc # custom ECC for PULP HCI IPs, make sure to include interface IPs when adding this target
+  # custom ECC for PULP HCI IPs, make sure to include interface IPs when adding this target
+  - target: hci_ecc
     files:
       - rtl/BUS_enc_dec/hci_core_intf_ecc_dec.sv
       - rtl/BUS_enc_dec/hci_core_intf_ecc_enc.sv
       - rtl/BUS_enc_dec/hci_mem_intf_ecc_dec.sv
       - rtl/BUS_enc_dec/hci_mem_intf_ecc_enc.sv
-  - target: pulp_ecc # custom ECC for PULP (pulp_soc) interface IPs, make sure to include interface IPs when adding this target
+
+  # custom ECC for PULP (pulp_soc) interface IPs, make sure to include interface IPs when adding this target
+  - target: pulp_ecc
     files:
       - rtl/BUS_enc_dec/PE_XBAR_bus_ecc_dec.sv
       - rtl/BUS_enc_dec/PE_XBAR_bus_ecc_enc.sv
       - rtl/BUS_enc_dec/TCDM_XBAR_bus_ecc_dec.sv
       - rtl/BUS_enc_dec/TCDM_XBAR_bus_ecc_enc.sv
       - rtl/BUS_enc_dec/XBAR_DEMUX_BUS_ecc_dec.sv
       - rtl/BUS_enc_dec/XBAR_DEMUX_BUS_ecc_enc.sv
-  - rtl/TMR_voter_detect.sv
-    # Level 2
-  - rtl/bitwise_TMR_voter.sv
-  - rtl/ecc_wrap/ecc_manager.sv
+
   - target: deprecated
     files:
-      - rtl/ecc_wrap/ecc_sram_wrap.sv
-  - rtl/ecc_wrap/ecc_sram.sv
-    # Level 3
-  - include_dirs:
-      - rtl/ODRG_unit
+      - rtl/deprecated/ecc_sram_wrap.sv
+
+  - target: any(deprecated, ODRG)
+    include_dirs:
+      - rtl/deprecated/ODRG_unit
     files:
-      - rtl/ODRG_unit/ODRG_unit.sv
-  - include_dirs:
-      - rtl/pulpissimo_tcls
+      - rtl/deprecated/ODRG_unit/odrg_manager_reg_pkg.sv
+      - rtl/deprecated/ODRG_unit/triple_core_barrier.sv
+      - rtl/deprecated/ODRG_unit/odrg_manager_reg_top.sv
+      - rtl/deprecated/ODRG_unit/ODRG_unit.sv
+
+  - target: any(deprecated, pulpissimo_tcls)
+    include_dirs:
+      - rtl/deprecated/pulpissimo_tcls
     files:
-      - rtl/pulpissimo_tcls/TCLS_unit.sv
+      - rtl/deprecated/pulpissimo_tcls/tcls_manager_reg_pkg.sv
+      - rtl/deprecated/pulpissimo_tcls/tcls_manager_reg_top.sv
+      - rtl/deprecated/pulpissimo_tcls/TCLS_unit.sv
+
+  - target: any(deprecated, HMR_wrap)
+    files:
+      - rtl/HMR/rapid_recovery/DMR_address_generator.sv
+      - rtl/deprecated/HMR_wrap.sv
+
   - target: test
     files:
       - test/tb_ecc_scrubber.sv
@@ -94,9 +135,9 @@ sources:
 
 vendor_package:
   - name: lowrisc_opentitan
-    target_dir: "util/lowrisc_opentitan"
+    target_dir: "rtl/deprecated/util/lowrisc_opentitan"
     upstream: { git: "https://github.com/lowRISC/opentitan.git", rev: "cfcfbce85e182c127b8c4be5cd8bf531e0a4d927" }
-    patch_dir: "util/patches"
+    patch_dir: "rtl/deprecated/util/patches"
     mapping:
       - {from: 'util/design/secded_gen.py', to: 'util/design/secded_gen.py', patch_dir: 'lowrisc_secded_gen'}
       - {from: 'util/design/data/', to: 'util/design/data/', patch_dir: 'lowrisc_data_dir'}

CHANGELOG.md

@@ -7,11 +7,14 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased
 ### Added
 - Add ECC correctors
+- Add `HMR` unit
 
 ### Changed
 - Replace vendor.py script with bender vendor for ECC modules
 - Update `ecc_manager` for configurability
 - Update secded testbench to use correctors and fix error injection
+- Deprecate `ODRG`, superceeded by HMR
+- Deprecate `pulpissimo_tcls`, superceeded by HMR
 
 ## 0.5.1 - 2023-04-12
 ### Added

Makefile

@@ -20,41 +20,111 @@ REG_PATH = $(shell $(BENDER) path register_interface)
 # REG_PATH = ../register_interface
 REG_TOOL = $(REG_PATH)/vendor/lowrisc_opentitan/util/regtool.py
 
-HJSON_ODRG = rtl/ODRG_unit/ODRG_unit.hjson
-HJSON_TCLS = rtl/pulpissimo_tcls/TCLS_unit.hjson
+HJSON_HMR = rtl/HMR/regs/HMR_regs.hjson
+HJSON_HMR_core = rtl/HMR/regs/HMR_core_regs.hjson
+HJSON_HMR_dmr = rtl/HMR/regs/HMR_dmr_regs.hjson
+HJSON_HMR_tmr = rtl/HMR/regs/HMR_tmr_regs.hjson
 HJSON_ECC = rtl/ecc_wrap/ecc_sram_wrapper.hjson
 
-TARGET_DIR_ODRG = rtl/ODRG_unit
-TARGET_DIR_TCLS = rtl/pulpissimo_tcls
+TARGET_DIR_HMR = rtl/HMR/regs
 TARGET_DIR_ECC = rtl/ecc_wrap
 
-.PHONY: gen_ODRG gen_TCLS gen_ecc_registers gen_ECC
-gen_ODRG:
-	python $(REG_TOOL) $(HJSON_ODRG) -t $(TARGET_DIR_ODRG) -r
-	python $(REG_TOOL) $(HJSON_ODRG) -d > $(TARGET_DIR_ODRG)/doc.md
-	python $(REG_TOOL) $(HJSON_ODRG) -D > $(TARGET_DIR_ODRG)/ODRG.h
+define HMR_H_HEADER_STRING
+/*
+ * Copyright (C) 2023 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
 
-gen_TCLS:
-	python $(REG_TOOL) $(HJSON_TCLS) -t $(TARGET_DIR_TCLS) -r
-	python $(REG_TOOL) $(HJSON_TCLS) -d > $(TARGET_DIR_TCLS)/doc.md
-	python $(REG_TOOL) $(HJSON_TCLS) -D > $(TARGET_DIR_TCLS)/TCLS.h
+#ifndef __ARCHI_HMR_HMR_V1_H__
+#define __ARCHI_HMR_HMR_V1_H__
+
+#define HMR_IN_INTERLEAVED 1
+
+#define HMR_TOP_OFFSET 0x000
+#define HMR_CORE_OFFSET   0x100
+#define HMR_DMR_OFFSET    0x200
+#define HMR_TMR_OFFSET    0x300
+
+#define HMR_CORE_INCREMENT 0x010
+#define HMR_CORE_SLL       0x004
+#define HMR_DMR_INCREMENT  0x010
+#define HMR_DMR_SLL        0x004
+#define HMR_TMR_INCREMENT  0x010
+#define HMR_TMR_SLL        0x004
+\n
+endef
+define HMR_H_FINAL_STRING
+\n\n
+#endif // __ARCHI_HMR_HMR_V1_H__
+
+endef
+export HMR_H_HEADER_STRING
+export HMR_H_FINAL_STRING
+
+.PHONY: gen_HMR gen_ecc_registers gen_ECC
+
+gen_HMR:
+	python $(REG_TOOL) $(HJSON_HMR) -t $(TARGET_DIR_HMR) -r
+	python $(REG_TOOL) $(HJSON_HMR) -d > $(TARGET_DIR_HMR)/doc.html
+	python $(REG_TOOL) $(HJSON_HMR) --doc > $(TARGET_DIR_HMR)/doc.md
+	python $(REG_TOOL) $(HJSON_HMR_core) -t $(TARGET_DIR_HMR) -r
+	python $(REG_TOOL) $(HJSON_HMR_dmr) -t $(TARGET_DIR_HMR) -r
+	python $(REG_TOOL) $(HJSON_HMR_tmr) -t $(TARGET_DIR_HMR) -r
+
+	@printf "$$HMR_H_HEADER_STRING" > $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "\n\n" >> $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR_core) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "\n\n" >> $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR_dmr) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "\n\n" >> $(TARGET_DIR_HMR)/hmr_v1.h
+	python $(REG_TOOL) $(HJSON_HMR_tmr) -D >> $(TARGET_DIR_HMR)/hmr_v1.h
+	@printf "$$HMR_H_FINAL_STRING" >> $(TARGET_DIR_HMR)/hmr_v1.h
 
 gen_ecc_registers:
 	python $(REG_TOOL) $(HJSON_ECC) -t $(TARGET_DIR_ECC) -r
 	python $(REG_TOOL) $(HJSON_ECC) -d > $(TARGET_DIR_ECC)/doc.md
 	python $(REG_TOOL) $(HJSON_ECC) -D > $(TARGET_DIR_ECC)/ECC.h
 
-gen_ECC:
-	$(BENDER) vendor init
-	cd util/lowrisc_opentitan && ./util/design/secded_gen.py --no_fpv --outdir ../../rtl/lowrisc_ecc
-
 bender:
 ifeq (,$(wildcard ./bender))
 	curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \
-		| bash -s -- 0.27.1
+		| bash -s -- 0.27.3
 	touch bender
 endif
 
 .PHONY: bender-rm
 bender-rm:
 	rm -f bender
+
+# deprecated
+.PHONY: gen_ODRG gen_TCLS
+HJSON_ODRG = rtl/deprecated/ODRG_unit/ODRG_unit.hjson
+HJSON_TCLS = rtl/deprecated/pulpissimo_tcls/TCLS_unit.hjson
+TARGET_DIR_ODRG = rtl/deprecated/ODRG_unit
+TARGET_DIR_TCLS = rtl/deprecated/pulpissimo_tcls
+
+gen_ODRG:
+	python $(REG_TOOL) $(HJSON_ODRG) -t $(TARGET_DIR_ODRG) -r
+	python $(REG_TOOL) $(HJSON_ODRG) -d > $(TARGET_DIR_ODRG)/doc.md
+	python $(REG_TOOL) $(HJSON_ODRG) -D > $(TARGET_DIR_ODRG)/ODRG.h
+
+gen_TCLS:
+	python $(REG_TOOL) $(HJSON_TCLS) -t $(TARGET_DIR_TCLS) -r
+	python $(REG_TOOL) $(HJSON_TCLS) -d > $(TARGET_DIR_TCLS)/doc.md
+	python $(REG_TOOL) $(HJSON_TCLS) -D > $(TARGET_DIR_TCLS)/TCLS.h
+
+gen_ECC:
+	$(BENDER) vendor init
+	cd rtl/deprecated/util/lowrisc_opentitan && ./util/design/secded_gen.py --no_fpv --outdir ../../lowrisc_ecc

README.md

@@ -2,11 +2,35 @@
 
 This repository contains various modules used to add redundancy.
 
+## Hybrid-Modular Redundancy (HMR)
+The `hmr_unit` is designed as a configurable bridge between multiple cores and the system, allowing for independent or lock-step operation, either in DMR or TMR mode. Further recovery mechanisms are implemented, including a SW-based recovery mechanism when in TMR mode with an interrupt being triggered on an error, a rapid recovery mechanism to automatically backup and refill the state with correct values, and in the future a checkpoint-based recovery mechanism.
+
+### Testing
+The HMR unit has been integrated in the [PULP cluster](https://github.com/pulp-platform/pulp_cluster/tree/michaero/hmr_merge) and the [Safety Island](https://github.com/pulp-platform/safety_island) in different configurations.
+
+### Citing
+If you are using HMR in your academic work you can cite us:
+```BibTeX
+@article{10.1145/3635161,
+author = {Rogenmoser, Michael and Tortorella, Yvan and Rossi, Davide and Conti, Francesco and Benini, Luca},
+title = {Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space},
+year = {2023},
+publisher = {Association for Computing Machinery},
+address = {New York, NY, USA},
+issn = {2378-962X},
+url = {https://doi.org/10.1145/3635161},
+doi = {10.1145/3635161},
+abstract = {Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely expensive, and developing inflexible architectural and microarchitectural modifications to introduce modular redundancy within a system leads to significant area increase and performance degradation. To mitigate the overheads of traditional radiation hardening and modular redundancy approaches, we present a novel Hybrid Modular Redundancy (HMR) approach, a redundancy scheme that features a cluster of RISC-V processors with a flexible on-demand dual-core and triple-core lockstep grouping of computing cores with runtime split-lock capabilities. Further, we propose two recovery approaches, software-based and hardware-based, trading off performance and area overhead. Running at 430MHz, our fault-tolerant cluster achieves up to 1160MOPS on a matrix multiplication benchmark when configured in non-redundant mode and 617 and 414 MOPS in dual and triple mode, respectively. A software-based recovery in triple mode requires 363 clock cycles and occupies 0.612 mm2, representing a 1.3\% area overhead over a non-redundant 12-core RISC-V cluster. As a high-performance alternative, a new hardware-based method provides rapid fault recovery in just 24 clock cycles and occupies 0.660 mm2, namely ∼ 9.4\% area overhead over the baseline non-redundant RISC-V cluster. The cluster is also enhanced with split-lock capabilities to enter one of the available redundant modes with minimum performance loss, allowing execution of a mission-critical portion of code when in independent mode, or a performance section when in a reliability mode, with <400 clock cycles overhead for entry and exit. The proposed system is the first to integrate these functionalities on an open-source RISC-V-based compute device, enabling finely tunable reliability vs. performance trade-offs.},
+note = {Just Accepted},
+journal = {ACM Trans. Cyber-Phys. Syst.},
+month = {nov}
+}
+```
+
 ## On-Demand Redundancy Grouping (ODRG_unit)
 The `ODRG_unit` is designed as a configurable bridge between three ibex cores, allowing for independent operation or lock-step operation with majority voting, triggering an interrupt in case a mismatch is detected. It uses lowrisc's reggen tool to generate the required configuration registers.
 
-### Testing
-ODRG is integrated in the [PULP cluster](https://github.com/pulp-platform/pulp_cluster/tree/space_pulp) and the [PULP](https://github.com/pulp-platform/pulp/tree/space_pulp) system. To test, please use the `space_pulp` branch.
+ODRG has been superceeded by HMR, as HMR integrates all ODRG features. To simplify maintenance, only one is included. If you would like to inspect the code, please check out the tag `v0.5.1`.
 
 ### Citing
 If you are using ODRG in your academic work you can cite us:
@@ -27,7 +51,7 @@ If you are using ODRG in your academic work you can cite us:
 
 To re-generate regfile, run following command in the root directory of this repo.
 ```bash
-make gen_ODRG
+make gen_HMR
 ```
 This will generate the register file SV-code, its corresponding C-code and documentation using lowrisc's reggen tool via the pulp register-interface repository.
 
@@ -59,4 +83,4 @@ To run tests, execute the following command:
 ./run_tests.sh
 ```
 
-A bender installation >=v0.27 is required.
+A [bender](https://github.com/pulp-platform/bender) installation >=v0.27 is required.