Parameterized ECC Encoder, Corrector and Register

.gitignore

@@ -6,5 +6,6 @@ modelsim.ini
 /working_dir
 /work
 vsim.log
+vsim.wlf
 vcom.log
 transcript

Bender.yml

@@ -1,32 +1,73 @@
 package:
   name: redundancy_cells
-  authors: 
+  authors:
     - "Michael Rogenmoser <michaero@iis.ee.ethz.ch>"
+    - "Luca Rufer <lrufer@student.ethz.ch>"
 
 dependencies:
   tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.3 }
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
   register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1 }
   common_cells:        { git: "https://github.com/pulp-platform/common_cells.git", version: 1.24.0 }
 
+export_include_dirs:
+  - rtl/ECC_reg/include
 sources:
     # Source files grouped in levels. Files in level 0 have no dependencies on files in this
     # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
     # levels 1 and 0, etc. Files within a level are ordered alphabetically.
     # Level 0
   - rtl/ODRG_unit/odrg_manager_reg_pkg.sv
+  - rtl/dmr/DMR_handshake_fork.sv
+  - rtl/dmr/DMR_handshake_join.sv
+  - rtl/dmr/DMR_instr_join_fork.sv
+  - rtl/dmr/DMR_interrupt_fork.sv
+  - rtl/dmr/DMR_write_mux.sv
+  - rtl/ECC_reg/hamming.sv
+  - rtl/ECC_reg/tmr_reg.sv
   - rtl/ecc_wrap/ecc_manager_reg_pkg.sv
   - rtl/ecc_wrap/ecc_manager_2_reg_pkg.sv
   - rtl/ecc_wrap/ecc_manager_8_reg_pkg.sv
   - rtl/pulpissimo_tcls/tcls_manager_reg_pkg.sv
+  - rtl/lowrisc_ecc/prim_secded_4_1_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_4_1_dec.svq
+  - rtl/lowrisc_ecc/prim_secded_4_1_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_8_4_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_8_4_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_8_4_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_13_8_cor.sv
   - rtl/lowrisc_ecc/prim_secded_13_8_dec.sv
   - rtl/lowrisc_ecc/prim_secded_13_8_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_16_11_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_16_11_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_16_11_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_22_16_cor.sv
   - rtl/lowrisc_ecc/prim_secded_22_16_dec.sv
   - rtl/lowrisc_ecc/prim_secded_22_16_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_28_22_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_28_22_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_28_22_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_32_26_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_32_26_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_32_26_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_39_32_cor.sv
   - rtl/lowrisc_ecc/prim_secded_39_32_dec.sv
   - rtl/lowrisc_ecc/prim_secded_39_32_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_64_57_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_64_57_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_64_57_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_72_64_cor.sv
   - rtl/lowrisc_ecc/prim_secded_72_64_dec.sv
   - rtl/lowrisc_ecc/prim_secded_72_64_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_128_120_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_128_120_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_128_120_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_256_247_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_256_247_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_256_247_enc.sv
+  - rtl/lowrisc_ecc/prim_secded_512_502_cor.sv
+  - rtl/lowrisc_ecc/prim_secded_512_502_dec.sv
+  - rtl/lowrisc_ecc/prim_secded_512_502_enc.sv
   - rtl/lowrisc_ecc/prim_secded_pkg.sv
   - rtl/ODRG_unit/triple_core_barrier.sv
   - rtl/TMR_voter.sv
@@ -57,14 +98,19 @@ sources:
       - rtl/BUS_enc_dec/TCDM_XBAR_bus_ecc_enc.sv
       - rtl/BUS_enc_dec/XBAR_DEMUX_BUS_ecc_dec.sv
       - rtl/BUS_enc_dec/XBAR_DEMUX_BUS_ecc_enc.sv
+  - rtl/ECC_reg/ecc_enc.sv
+  - rtl/ECC_reg/ecc_cor.sv
   - rtl/TMR_voter_detect.sv
     # Level 2
   - rtl/bitwise_TMR_voter.sv
+  - rtl/ECC_reg/ecc_reg.sv
   - rtl/ecc_wrap/ecc_manager.sv
   - rtl/ecc_wrap/ecc_manager_2.sv
   - rtl/ecc_wrap/ecc_manager_8.sv
   - rtl/ecc_wrap/ecc_sram_wrap.sv
     # Level 3
+  - rtl/ECC_reg/dmr_io_tmr_reg.sv
+    # Level 4
   - include_dirs:
       - rtl/ODRG_unit
     files:
@@ -75,11 +121,19 @@ sources:
       - rtl/pulpissimo_tcls/TCLS_unit.sv
   - target: test
     files:
+      # Level 0
+      - test/dmr/dmr_handshake.sv
+      - test/tb_ecc_enc_cor.sv
+      - test/tb_ecc_reg.sv
       - test/tb_ecc_scrubber.sv
       - test/tb_ecc_secded.sv
       - test/tb_ecc_sram.sv
+      - test/tb_tmr_reg.sv
       - test/tb_tmr_voter.sv
       - test/tb_tmr_voter_detect.sv
       - test/tb_tmr_word_voter.sv
       - test/tb_bitwise_tmr_voter.sv
-
+      # Level 1
+      - test/tb_dmr_handshake_fork.sv
+      - test/tb_dmr_handshake_join.sv
+      - test/tb_dmr_handshake_fork_join_fork.sv

CHANGELOG.md

@@ -6,6 +6,14 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ## Unreleased
 
+### Added
+- Add secded ECC corrector
+- Add encoder and corrector with parameterizable data width and code
+- Add ECC protected register
+
+### Changed
+- Update secded testbench to use correctors and fix error injection
+
 ## 0.5.0 - 2022-12-21
 
 ### Added

rtl/ECC_reg/dmr_io_tmr_reg.sv

@@ -0,0 +1,121 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// Description: Flipflop with TMR state protection and integrated voter.
+//              The FF has two inputs that are to be used in DMR circuits to
+//              protect combinatorial logic. The 'dmr_err_o' signal indicates
+//              that the input signals don't match. The 'no_load_i' signal
+//              is used to prevent the new input from being loaded into the FF.
+//              it is advised to connect 'dmr_err_o' ORed with other signals
+//              to 'no_load_i' (this is NOT done internally).
+//              The 'voter_err_o' signal indicates a voter mismatch. It can
+//              be caused by an SEU in a Flip-Flop or an SET in an internal MUX
+//              or in the voter.
+//              The DMR checking can be disabled by setting 'no_load_i' to 0.
+//              However, loading new data when the inputs don't match will cause
+//              a voter mismatch one cycle later. Data input 1 takes priority
+//              over data input 2.
+// Note: This implementation does not feature the LOAD-type FFs, as this can be
+//       controlled via the 'no_load_i' signal.
+// Note: Special care has to be taken during layout that redundant parts of this
+//       module are not optimized away.
+
+// Hint: Use the macros in 'tmr_registers.svh' instead of using this module directly.
+
+`include "common_cells/registers.svh"
+
+module dmr_io_tmr_reg #(
+  // Data Settings
+  parameter int unsigned DataWidth = 0,
+  // FF Settings
+  parameter bit HasReset = 1,
+  parameter bit AsynchronousReset = 1,
+  parameter bit ActiveLowReset = 1
+) (
+  // Clock and reset
+  input  logic                clk_i,
+  input  logic                rst_ni,
+  // Data Input
+  input  logic[DataWidth-1:0] data_1_i,
+  input  logic[DataWidth-1:0] data_2_i,
+  // Data Output
+  output logic[DataWidth-1:0] data_1_o,
+  output logic[DataWidth-1:0] data_2_o,
+  // Error and Control signals
+  output logic                dmr_err_o,
+  input  logic                no_load_i,
+  output logic                voter_err_o,
+  // FF ports
+  input  logic[DataWidth-1:0] reset_value_i
+);
+
+logic [3*DataWidth-1:0] data_d, data_q, reset_value;
+
+/*****************************
+ *  Compare and Select Data  *
+ *****************************/
+
+assign dmr_err_o = (data_1_i != data_2_i);
+
+assign data_d = (no_load_i) ? data_q : {3{data_1_i}};
+
+/*****************
+ *   Flip-Flop   *
+ *****************/
+
+assign reset_value = {3{reset_value_i}};
+
+logic rst;
+assign rst = ~rst_ni;
+
+if ( HasReset &&  AsynchronousReset &&  ActiveLowReset) begin
+  `FF(data_q, data_d, reset_value, clk_i, rst_ni)
+end else if ( HasReset &&  AsynchronousReset && ~ActiveLowReset) begin
+  `FFAR(data_q, data_d, reset_value, clk_i, rst)
+end else if ( HasReset && ~AsynchronousReset && ~ActiveLowReset) begin
+  `FFSR(data_q, data_d, reset_value, clk_i, rst)
+end else if ( HasReset && ~AsynchronousReset &&  ActiveLowReset) begin
+  `FFSRN(data_q, data_d, reset_value, clk_i, rst_ni)
+end else if ( ~HasReset) begin
+  `FFNR(data_q, data_d, clk_i)
+end
+
+/*******************
+ *    Vote Data    *
+ *******************/
+
+logic [2:0] voter_err_1, voter_err_2;
+
+// Create two independent voters to prevent common-mode DMR faults
+bitwise_TMR_voter #(
+  .DataWidth   ( DataWidth                      )
+) i_voter_1 (
+  .a_i         ( data_q[0*DataWidth+:DataWidth] ),
+  .b_i         ( data_q[1*DataWidth+:DataWidth] ),
+  .c_i         ( data_q[2*DataWidth+:DataWidth] ),
+  .majority_o  ( data_1_o                       ),
+  .error_o     (                                ),
+  .error_cba_o ( voter_err_1                    )
+);
+
+bitwise_TMR_voter #(
+  .DataWidth   ( DataWidth                      )
+) i_voter_2 (
+  .a_i         ( data_q[0*DataWidth+:DataWidth] ),
+  .b_i         ( data_q[1*DataWidth+:DataWidth] ),
+  .c_i         ( data_q[2*DataWidth+:DataWidth] ),
+  .majority_o  ( data_2_o                       ),
+  .error_o     (                                ),
+  .error_cba_o ( voter_err_2                    )
+);
+
+assign voter_err_o = |voter_err_1 | |voter_err_2;
+
+endmodule