[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)#10025
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[ExportVerilog] Fix XMR paths for inner symbols in generate.case (#9972)#10025
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Fixes #9972 |
…m#9972) - Emit generate/case scope names before instance segments, matching `GenerateOp` / `GenerateCaseOp` emission (including `legalizeName` order for case labels)
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uenoku
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Mar 24, 2026
uenoku
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Thank you for working on this!
…#10025) - Follow the reviewer's suggestions
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@uenoku Thanks for the review! I’ve addressed the comments and pushed updates. Could you please take another look when you have a chance? Thanks!! |
uenoku
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Mar 25, 2026
fix nit: please avoid unnecessary allocation of strings Co-authored-by: Hideto Ueno <uenoku.tokotoko@gmail.com>
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The CI seems to be failing, but 'Conversion/ExportVerilog/sv-dialect.mlir' tests pass on my local machine. @uenoku Would you be able to help take a look when you have a moment? Thanks in advance! |
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GenerateOp/GenerateCaseOpemission (includinglegalizeNameorder for case labels)