Yosys 0.57

Yosys 0.56 .. Yosys 0.57

• New commands and options

  • Added "-initstates" option to "abstract" pass.
  • Added "-set-assumes" option to "equiv_induct"
    and "equiv_simple" passes.
  • Added "-always" option to "raise_error" pass.
  • Added "-hierarchy" option to "stat" pass.
  • Added "-noflatten" option to "synth_quicklogic" pass.

• Various

  • smtbmc: Support skipping steps in cover mode.
  • write_btor: support $buf.
  • read_verilog: support package import.

Yosys 0.56

Yosys 0.55 .. Yosys 0.56

• New commands and options

  • Added "-unescape" option to "rename" pass.
  • Added "-assert2cover" option to "chformal" pass.
  • Added "linecoverage" pass to generate lcov report from selection.
  • Added "opt_hier" pass to enable hierarchical optimization.
  • Added "-hieropt" option to "synth" pass.
  • Added "-expect-return", "-err-grep" and "-suffix" options
    to "bugpoint" pass.
  • Added "raise_error" dev pass.

• Various

  • Added groups to command reference documentation.
  • Added bugpoint guide to documentation.
  • verific: correctly reset Verific flags after import.

Yosys 0.55

Yosys 0.54 .. Yosys 0.55

• Various
  • read_verilog: Implemented SystemVerilog unique/priority if.
  • "attrmap" pass is able to alter memory attributes.
  • verific: Support SVA followed-by operator in cover mode.

Yosys 0.54

Yosys 0.53 .. Yosys 0.54

• New commands and options

  • Added "-genlib" option to "abc_new" and "abc9_exe" passes.
  • Added "-verbose" and "-quiet" options to "libcache" pass.
  • Added "-no-sort" option to "write_aiger" pass.

• Various

  • Added "muldiv_c" peepopt.
  • Accept (and ignore) SystemVerilog unique/priority if.
  • "read_verilog" copy inout ports in and out of functions/tasks.
  • Enable single-bit vector wires in RTLIL.

• Xilinx support

  • Single-port URAM mapping to support memories 2048 x 144b

Yosys 0.53

Yosys 0.52 .. Yosys 0.53

• New commands and options

  • Added "constmap" pass for technology mapping of coarse constant value.
  • Added "timeest" pass to estimate the critical path in clock domain.
  • Added "-blackbox" option to "cutpoint" pass to cut all instances of
    blackboxes.
  • Added "-noscopeinfo" option to "cutpoint" pass.
  • Added "-nocleanup" option to "flatten" pass to prevent removal of
    unused submodules.
  • Added "-declockgate" option to "formalff" pass that turns clock
    gating into clock enables.

• Various

  • Added "$scopeinfo" cells to preserve information during "cutpoint" pass.
  • Added dataflow tracking documentation.
  • share: Restrict activation patterns to potentially relevant signal.
  • liberty: More robust parsing.
  • verific: bit blast RAM if using mem2reg attribute.

Yosys 0.52

Yosys 0.51 .. Yosys 0.52

• New commands and options

  • Added "-pattern-limit" option to "share" pass to limit analysis effort.
  • Added "libcache" pass to control caching of technology library
    data parsed from liberty files.
  • Added "read_verilog_file_list" to parse verilog file list.

• Various

  • Added $macc_v2 cell.
  • Improve lexer performance and zlib support for "read_liberty".
  • opt_expr: optimize pow of 2 cells.

Yosys 0.51

Yosys 0.50 .. Yosys 0.51

• New commands and options

  • Added "abstract" pass to allow reducing and never increasing
    the constraints on a circuit's behavior in a formal verification setting.

• Various

  • "splitcells" pass now splits "aldff" cells.
  • FunctionalIR documentation

• QuickLogic support

  • Added IOFF inference for qlf_k6n10f

• Intel support

  • Fixed RAM and DSP support.
  • Overall performance improvement for "synth_intel".

Yosys 0.50

Yosys 0.49 .. Yosys 0.50

• Various
  • "write_verilog" emits "$check" cell names as labels.

Yosys 0.49

Yosys 0.48 .. Yosys 0.49

• Various

  • "$scopeinfo" cells are now part of JSON export by default.
  • Added option to specify hierarchical separator for "flatten".
  • Improved "wreduce" to handle more cases of operator size reduction.
  • Updated hashing interface, see docs/source/yosys_internals/hashing.rst
    for breaking API changes.

• New commands and options

  • Added "-noscopeinfo" option to "json" and "write_json" pass.

Yosys 0.48

Yosys 0.47 .. Yosys 0.48

• Various

  • Removed "read_ilang" deprecated pass.
  • Enhanced boxing features in the experimental "abc_new" command.
  • Added new Tcl methods for design inspection.
  • Added clock enable inference to "dfflibmap".
  • Added a Han-Carlson and Sklansky option for $lcu mapping.

• New commands and options

  • Added "-nopeepopt" option to "clk2fflogic" pass.
  • Added "-liberty" and "-dont_use" options to "clockgate" pass.
  • Added "-ignore_buses" option to "read_liberty" pass.
  • Added "-dont_map" option to "techmap" pass.
  • Added "-selected" option to "write_json" pass.
  • Added "wrapcell" command for creating wrapper modules
    around selected cells.
  • Added "portarcs" command for deriving propagation timing arcs.
  • Added "setenv" command for setting environment variables.

• Gowin support

  • Added "-family" option to "synth_gowin" pass.
  • Cell definitions split by family.

• Verific support

  • Improved blackbox support.