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Pull requests: YosysHQ/yosys

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Pull requests list

Make attrmap able to alter memory attributes as well
#5162 opened Jun 4, 2025 by mmicko Loading…
verilog: improve string literal matching speed (fixes #5076) merge-after-release Merge: PR should not be included in the next release
#5160 opened Jun 1, 2025 by garytwong Loading…
verilog: implement SystemVerilog unique/unique0/priority if semantics. merge-soon Merge: PR will be merged at the end of the next work day unless concerns are raised
#5152 opened May 30, 2025 by garytwong Loading…
Docs: Add bugpoint guide
#5139 opened May 22, 2025 by KrystalDelusion Loading…
Maintain port ordering for functional backend
#5133 opened May 21, 2025 by KrystalDelusion Loading…
Update verilog_frontend.cc
#5102 opened May 7, 2025 by KrystalDelusion Loading…
rename: add -move-to-cell option in -wire mode
#5100 opened May 7, 2025 by jix Loading…
autoname: Check for potential overflow
#5081 opened May 1, 2025 by KrystalDelusion Loading…
Updates to bugpoint
#5068 opened Apr 28, 2025 by KrystalDelusion Loading…
5 of 6 tasks
more detailed Stat command
#5054 opened Apr 23, 2025 by suisseWalter Draft
Updating test_cell
#5024 opened Apr 15, 2025 by KrystalDelusion Loading…
7 tasks done
dump: add --sorted flag
#5003 opened Apr 8, 2025 by widlarizer Loading…
1 task
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