dma-mux support #5
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Add devicetree binding for Sophgo CV1800B SoC reset controller. Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Ze Huang <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
Add reset controller support for Sophgo CV1800B SoC reusing the reset-simple driver. Signed-off-by: Jisheng Zhang <[email protected]>
Add the reset device tree node and reset phandle to uart nodes. Although, the resets are deasserted by default. Add them for completeness. Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: AnnanLiu <[email protected]> Signed-off-by: Ze Huang <[email protected]>
…driver Commit 8ec99b0 ("irqchip/sifive-plic: Convert PLIC driver into aplatform driver")[1] broke timer initialization because the PLIC IRQdomain is no longer available in a TIMER_OF_DECLARE. The following error was observed: [ 0.024789] irq: no irq domain found for interrupt-controller@70000000 ! Following [2], fix this by moving the IRQ handling code to a platform driver. Tested by changing system clocksource. Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/ [1] Link: https://lore.kernel.org/linux-riscv/[email protected]/ [2] Signed-off-by: Ze Huang <[email protected]>
Signed-off-by: Ze Huang <[email protected]>
dw_apb_timer_of cannot get clock resource without name "timer". Signed-off-by: Ze Huang <[email protected]>
The DMA IP of Sophgo CV18XX/SG200X is based on a DW AXI CORE, with an additional channel remap register located in the top system control area. The DMA channel is exclusive to each core. In addition, the DMA multiplexer is a subdevice of system controller, so this binding only contains necessary properties for the multiplexer itself. Add the dmamux binding for CV18XX/SG200X series SoC. Signed-off-by: Inochi Amaoto <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
Sophgo CV18XX/SG200X use DW AXI CORE with a multiplexer for remapping its request lines. The multiplexer supports at most 8 request lines. Add driver for Sophgo CV18XX/SG200X DMA multiplexer. Signed-off-by: Inochi Amaoto <[email protected]>
On platforms other than Intel KeemBay AxiDMA, apb_regs are not supported. Add a check on apb_regs to prevent unnecessary calls to dw_axi_dma_set_hw_channel and dw_axi_dma_set_byte_halfword.
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you tested it on loopback mode. did you? |
The Duo DMA controller supports a 32-bit bus width. If the configuration is incorrect, the DMA block transfer size may exceed the hardware's maximum supported size, resulting in data loss during transfers. Link to tests: https://gist.github.com/Sutter099/4fa99bb2d89e5af975983124704b3861 Signed-off-by: Ze Huang <[email protected]>
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Yes, tested in mem2mem mode. https://gist.github.com/Sutter099/4fa99bb2d89e5af975983124704b3861 |
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This series of patches adds support for DMA multiplexing (DMA-MUX) on the CV18XX/SG200X platform.
The CV18XX/SG200X platform uses the DesignWare AXI DMA IP, which includes an additional channel mapping register in the system control region. This register is used to configure the physical DMA channels to different peripherals. Each core has exclusive access to its DMA channels.
Testing was performed with UART1 using following dts configs:
Both transmit and receive operations work correctly in DMA mode.