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Merged
merged 15 commits into from
Nov 22, 2025
+2,799 −2,399
Merged

Enhanced max slew fixing to remove large unfixed violations #8870

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e47c6aa
Enhanced max slew fixing to resolve large unfixed violations
precisionmoon Nov 15, 2025
c67319f
rebased flow tests
precisionmoon Nov 15, 2025
f2529a6
rebased CTS tests
precisionmoon Nov 15, 2025
96fa1ed
rebased one flow test
precisionmoon Nov 15, 2025
50c35f6
limited sizeup match to single fanouts only
precisionmoon Nov 18, 2025
37305e9
Merge remote-tracking branch 'origin/master' into secure-new-slew-fix
precisionmoon Nov 18, 2025
12c486c
consider max cap violations during sizing
precisionmoon Nov 19, 2025
7fa8002
Merge remote-tracking branch 'origin/master' into secure-new-slew-fix
precisionmoon Nov 19, 2025
dd520f4
fixed clang-tidy and rebased one flow test
precisionmoon Nov 19, 2025
0944ff0
Merge remote-tracking branch 'origin/master' into secure-new-slew-fix
precisionmoon Nov 20, 2025
d026bcf
Merge remote-tracking branch 'origin/master' into secure-new-slew-fix
precisionmoon Nov 20, 2025
e749264
fixed opto move update bug in repair_timing
precisionmoon Nov 20, 2025
ad54505
merged with master
precisionmoon Nov 21, 2025
8d5bf8a
changed C++20 codes to be backward compatible
precisionmoon Nov 21, 2025
9bccbcd
mpl/rsz: reinstate c++20 usage
maliberty Nov 22, 2025
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149 changes: 75 additions & 74 deletions src/cts/test/array.ok
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Original file line number Diff line number Diff line change
Expand Up @@ -125,22 +125,22 @@ Dummys used:
INV_X4: 1
[INFO RSZ-0058] Using max wire length 693um.
[INFO RSZ-0047] Found 41 long wires.
[INFO RSZ-0048] Inserted 117 buffers in 41 nets.
[INFO RSZ-0048] Inserted 165 buffers in 41 nets.
Placement Analysis
---------------------------------
total displacement 4255.5 u
total displacement 4186.7 u
average displacement 1.3 u
max displacement 143.4 u
original HPWL 192636.5 u
legalized HPWL 193564.6 u
original HPWL 192698.4 u
legalized HPWL 193625.0 u
delta HPWL 0 %

Clock clk
1.06 source latency inst_5_7/clk ^
-1.20 target latency inst_6_7/clk ^
1.03 source latency inst_5_4/clk ^
-1.18 target latency inst_6_4/clk ^
0.00 CRPR
--------------
-0.14 setup skew
-0.15 setup skew

Startpoint: inst_1_1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
Expand All @@ -152,76 +152,76 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk (in)
0.04 0.04 ^ wire8/Z (BUF_X8)
0.03 0.07 ^ wire7/Z (BUF_X16)
0.06 0.13 ^ load_slew6/Z (BUF_X8)
0.06 0.18 ^ wire5/Z (BUF_X16)
0.04 0.04 ^ wire9/Z (BUF_X8)
0.03 0.07 ^ wire8/Z (BUF_X16)
0.06 0.13 ^ wire6/Z (BUF_X8)
0.05 0.18 ^ wire5/Z (BUF_X16)
0.05 0.23 ^ wire4/Z (BUF_X16)
0.06 0.29 ^ wire3/Z (BUF_X32)
0.06 0.34 ^ wire2/Z (BUF_X32)
0.04 0.39 ^ wire1/Z (BUF_X32)
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 0.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 1.05 ^ wire10/Z (BUF_X8)
0.04 1.10 ^ wire9/Z (BUF_X8)
0.05 1.15 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
0.00 1.15 ^ inst_1_1/clk (array_tile)
0.21 1.36 ^ inst_1_1/e_out (array_tile)
0.00 1.36 ^ inst_2_1/w_in (array_tile)
1.36 data arrival time
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 1.05 ^ wire14/Z (BUF_X8)
0.05 1.10 ^ load_slew11/Z (BUF_X1)
0.03 1.13 ^ clkbuf_leaf_0_clk/Z (BUF_X4)
0.00 1.13 ^ inst_1_1/clk (array_tile)
0.21 1.35 ^ inst_1_1/e_out (array_tile)
0.00 1.35 ^ inst_2_1/w_in (array_tile)
1.35 data arrival time

5.00 5.00 clock clk (rise edge)
0.00 5.00 clock source latency
0.00 5.00 ^ clk (in)
0.04 5.04 ^ wire8/Z (BUF_X8)
0.03 5.07 ^ wire7/Z (BUF_X16)
0.06 5.13 ^ load_slew6/Z (BUF_X8)
0.06 5.18 ^ wire5/Z (BUF_X16)
0.04 5.04 ^ wire9/Z (BUF_X8)
0.03 5.07 ^ wire8/Z (BUF_X16)
0.06 5.13 ^ wire6/Z (BUF_X8)
0.05 5.18 ^ wire5/Z (BUF_X16)
0.05 5.23 ^ wire4/Z (BUF_X16)
0.06 5.29 ^ wire3/Z (BUF_X32)
0.06 5.34 ^ wire2/Z (BUF_X32)
0.04 5.39 ^ wire1/Z (BUF_X32)
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 5.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 6.05 ^ max_length12/Z (BUF_X8)
0.04 6.08 ^ wire11/Z (BUF_X8)
0.02 6.10 ^ inst_2_1/clk (array_tile)
0.00 6.10 clock reconvergence pessimism
-0.05 6.05 library setup time
6.05 data required time
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 6.04 ^ load_slew18/Z (BUF_X8)
0.03 6.07 ^ load_slew16/Z (BUF_X1)
0.00 6.07 ^ inst_2_1/clk (array_tile)
0.00 6.07 clock reconvergence pessimism
-0.05 6.02 library setup time
6.02 data required time
---------------------------------------------------------
6.05 data required time
-1.36 data arrival time
6.02 data required time
-1.35 data arrival time
---------------------------------------------------------
4.69 slack (MET)
4.67 slack (MET)


Startpoint: inst_2_1 (rising edge-triggered flip-flop clocked by clk)
Expand All @@ -234,74 +234,75 @@ Path Type: max
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk (in)
0.04 0.04 ^ wire8/Z (BUF_X8)
0.03 0.07 ^ wire7/Z (BUF_X16)
0.06 0.13 ^ load_slew6/Z (BUF_X8)
0.06 0.18 ^ wire5/Z (BUF_X16)
0.04 0.04 ^ wire9/Z (BUF_X8)
0.03 0.07 ^ wire8/Z (BUF_X16)
0.06 0.13 ^ wire6/Z (BUF_X8)
0.05 0.18 ^ wire5/Z (BUF_X16)
0.05 0.23 ^ wire4/Z (BUF_X16)
0.06 0.29 ^ wire3/Z (BUF_X32)
0.06 0.34 ^ wire2/Z (BUF_X32)
0.04 0.39 ^ wire1/Z (BUF_X32)
0.06 0.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 0.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 0.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 0.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.04 0.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 0.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 0.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 0.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 0.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 0.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 0.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 0.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 0.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 0.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 0.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 0.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 0.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 1.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 1.05 ^ max_length12/Z (BUF_X8)
0.04 1.08 ^ wire11/Z (BUF_X8)
0.02 1.10 ^ inst_2_1/clk (array_tile)
0.21 1.32 ^ inst_2_1/e_out (array_tile)
0.00 1.32 ^ inst_3_1/w_in (array_tile)
1.32 data arrival time
0.04 0.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 1.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 1.04 ^ load_slew18/Z (BUF_X8)
0.03 1.07 ^ load_slew16/Z (BUF_X1)
0.00 1.07 ^ inst_2_1/clk (array_tile)
0.21 1.28 ^ inst_2_1/e_out (array_tile)
0.00 1.28 ^ inst_3_1/w_in (array_tile)
1.28 data arrival time

5.00 5.00 clock clk (rise edge)
0.00 5.00 clock source latency
0.00 5.00 ^ clk (in)
0.04 5.04 ^ wire8/Z (BUF_X8)
0.03 5.07 ^ wire7/Z (BUF_X16)
0.06 5.13 ^ load_slew6/Z (BUF_X8)
0.06 5.18 ^ wire5/Z (BUF_X16)
0.04 5.04 ^ wire9/Z (BUF_X8)
0.03 5.07 ^ wire8/Z (BUF_X16)
0.06 5.13 ^ wire6/Z (BUF_X8)
0.05 5.18 ^ wire5/Z (BUF_X16)
0.05 5.23 ^ wire4/Z (BUF_X16)
0.06 5.29 ^ wire3/Z (BUF_X32)
0.06 5.34 ^ wire2/Z (BUF_X32)
0.04 5.39 ^ wire1/Z (BUF_X32)
0.06 5.45 ^ clkbuf_0_clk/Z (BUF_X4)
0.04 5.49 ^ clkbuf_1_0_0_clk/Z (BUF_X4)
0.04 5.53 ^ clkbuf_1_0_1_clk/Z (BUF_X4)
0.04 5.57 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.04 5.56 ^ clkbuf_1_0_2_clk/Z (BUF_X4)
0.03 5.60 ^ clkbuf_1_0_3_clk/Z (BUF_X4)
0.04 5.64 ^ clkbuf_1_0_4_clk/Z (BUF_X4)
0.03 5.67 ^ clkbuf_2_0_0_clk/Z (BUF_X4)
0.03 5.71 ^ clkbuf_2_0_1_clk/Z (BUF_X4)
0.03 5.74 ^ clkbuf_2_0_2_clk/Z (BUF_X4)
0.03 5.78 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 5.82 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.77 ^ clkbuf_2_0_3_clk/Z (BUF_X4)
0.04 5.81 ^ clkbuf_2_0_4_clk/Z (BUF_X4)
0.03 5.85 ^ clkbuf_3_0_0_clk/Z (BUF_X4)
0.03 5.88 ^ clkbuf_3_0_1_clk/Z (BUF_X4)
0.03 5.92 ^ clkbuf_3_0_2_clk/Z (BUF_X4)
0.04 5.96 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 6.01 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 6.05 ^ max_length12/Z (BUF_X8)
0.05 6.10 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
0.00 6.10 ^ inst_3_1/clk (array_tile)
0.00 6.10 clock reconvergence pessimism
-0.05 6.05 library setup time
6.05 data required time
0.04 5.95 ^ clkbuf_4_0_0_clk/Z (BUF_X4)
0.05 6.00 ^ clkbuf_4_0_1_clk/Z (BUF_X4)
0.04 6.04 ^ load_slew18/Z (BUF_X8)
0.04 6.08 ^ wire17/Z (BUF_X4)
0.04 6.12 ^ clkbuf_leaf_118_clk/Z (BUF_X4)
0.00 6.12 ^ inst_3_1/clk (array_tile)
0.00 6.12 clock reconvergence pessimism
-0.05 6.07 library setup time
6.07 data required time
---------------------------------------------------------
6.05 data required time
-1.32 data arrival time
6.07 data required time
-1.28 data arrival time
---------------------------------------------------------
4.73 slack (MET)
4.79 slack (MET)


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