Sdc fix invalid start point

[oharboe]

No description provided.

[maliberty]

Is this expected?

[oharboe]

I don't know if it is the intended OpenSTA behavior, but I think so. I think this is good 'nuf to commit for further study and development.

"all_registers" includes macros and OpenSTA includes the clock tree in the reg2out path group:

WNS for reg2reg is essentially unchanged(a few ps different).

>>> report_checks
Startpoint: io_ins_up_1[16] (input port)
Endpoint: ces_0_1/io_ins_up[16] (internal path endpoint)
Path Group: in2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00 v input external delay
   0.00    0.00 v io_ins_up_1[16] (in)
  10.94   10.94 v input1608/Y (BUFx3_ASAP7_75t_R)
   0.05   10.99 v ces_0_1/io_ins_up[16] (Element)
          10.99   data arrival time

  80.00   80.00   max_delay
   0.00   80.00   output external delay
          80.00   data required time
---------------------------------------------------------
          80.00   data required time
         -10.99   data arrival time
---------------------------------------------------------
          69.01   slack (MET)


Startpoint: REG_2$_DFF_P_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: io_lsbs_2 (output port)
Path Group: reg2out
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
 502.52  502.52   clock network delay (propagated)
   0.00  502.52 ^ REG_2$_DFF_P_/CLK (DFFHQNx1_ASAP7_75t_R)
  40.76  543.28 ^ REG_2$_DFF_P_/QN (DFFHQNx1_ASAP7_75t_R)
   7.04  550.32 v _078_/Y (INVx1_ASAP7_75t_R)
  13.63  563.94 v output2061/Y (BUFx3_ASAP7_75t_R)
   0.45  564.39 v io_lsbs_2 (out)
         564.39   data arrival time

  80.00   80.00   max_delay
   0.00   80.00   output external delay
          80.00   data required time
---------------------------------------------------------
          80.00   data required time
        -564.39   data arrival time
---------------------------------------------------------
        -484.39   slack (VIOLATED)


Startpoint: ces_1_1 (rising edge-triggered flip-flop clocked by clock)
Endpoint: ces_1_5 (rising edge-triggered flip-flop clocked by clock)
Path Group: reg2reg
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clock (rise edge)
 391.96  391.96   clock network delay (propagated)
   0.00  391.96 ^ ces_1_1/clock (Element)
 150.42  542.39 ^ ces_1_1/io_lsbOuts_7 (Element)
  34.37  576.76 ^ ces_1_2/io_lsbOuts_6 (Element)
  30.30  607.06 ^ ces_1_3/io_lsbOuts_5 (Element)
  29.89  636.95 ^ ces_1_4/io_lsbOuts_4 (Element)
   0.00  636.95 ^ ces_1_5/io_lsbIns_4 (Element)
         636.95   data arrival time

 250.00  250.00   clock clock (rise edge)
 322.79  572.79   clock network delay (propagated)
   4.34  577.13   clock reconvergence pessimism
         577.13 ^ ces_1_5/clock (Element)
  55.54  632.67   library setup time
         632.67   data required time
---------------------------------------------------------
         632.67   data required time
        -636.95   data arrival time
---------------------------------------------------------
          -4.28   slack (VIOLATED)

[oharboe]

@maliberty If you want to look at the design The-OpenROAD-Project/OpenROAD#7721