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lines changed Original file line number Diff line number Diff line change 4848 "compare" : " <="
4949 },
5050 "finish__timing__setup__ws" : {
51- "value" : 0.0 ,
51+ "value" : -440.47 ,
5252 "compare" : " >="
5353 },
5454 "finish__design__instance__area" : {
5555 "value" : 137967 ,
5656 "compare" : " <="
5757 },
5858 "finish__timing__drv__setup_violation_count" : {
59- "value" : 536 ,
59+ "value" : 605 ,
6060 "compare" : " <="
6161 },
6262 "finish__timing__drv__hold_violation_count" : {
6363 "value" : 100 ,
6464 "compare" : " <="
6565 },
6666 "finish__timing__wns_percent_delay" : {
67- "value" : -10.0 ,
67+ "value" : -111.1 ,
6868 "compare" : " >="
6969 }
7070}
Original file line number Diff line number Diff line change @@ -70,15 +70,14 @@ set clk_port [get_ports $clk_port_name]
7070create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
7171
7272set non_clk_inputs [all_inputs -no_clocks]
73- set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}]
7473
7574# Optimization targets: overconstrain by default and
7675# leave refinements to a more design specific constraints.sdc file.
7776#
7877# Minimum time for io-io, io-reg, reg-io paths in macro is on
7978# the order of 80ps for a small macro on ASAP7.
8079set_max_delay [expr { [info exists in2reg_max] ? $in2reg_max : 80 }] -from $non_clk_inputs -to [all_registers]
81- set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from $all_register_outputs -to [all_outputs]
80+ set_max_delay [expr { [info exists reg2out_max] ? $reg2out_max : 80 }] -from [all_registers] -to [all_outputs]
8281set_max_delay [expr { [info exists in2out_max] ? $in2out_max : 80 }] -from $non_clk_inputs -to [all_outputs]
8382
8483# This allows us to view the different groups
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