Merge pull request #3288 from Pinata-Consulting/sdc-simpler

maliberty · web-flow · commit 9c8c69e90cb3 · 2025-07-04T11:13:24.000Z
sdc: simplify
diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/aes/constraint.sdc b/flow/designs/asap7/aes/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/ethmac/constraint.sdc b/flow/designs/asap7/ethmac/constraint.sdc
@@ -3,7 +3,7 @@ set clk_period 1000
 set clk_io_pct 0.2
 set clk_port [get_ports $top_clk_name]
 create_clock -name $top_clk_name -period $clk_period $clk_port
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
 
diff --git a/flow/designs/asap7/ethmac_lvt/constraint.sdc b/flow/designs/asap7/ethmac_lvt/constraint.sdc
@@ -3,7 +3,7 @@ set clk_period 1000
 set clk_io_pct 0.2
 set clk_port [get_ports $top_clk_name]
 create_clock -name $top_clk_name -period $clk_period $clk_port
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $top_clk_name [all_outputs]
 
diff --git a/flow/designs/asap7/gcd/constraint.sdc b/flow/designs/asap7/gcd/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/ibex/constraint.sdc b/flow/designs/asap7/ibex/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/ibex/constraint_pos_slack.sdc b/flow/designs/asap7/ibex/constraint_pos_slack.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/riscv32i/constraint.sdc b/flow/designs/asap7/riscv32i/constraint.sdc
@@ -9,6 +9,6 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/asap7/uart/constraint.sdc b/flow/designs/asap7/uart/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf12/aes/constraint.sdc b/flow/designs/gf12/aes/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf12/gcd/constraint.sdc b/flow/designs/gf12/gcd/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf12/ibex/constraint.sdc b/flow/designs/gf12/ibex/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf12/jpeg/constraint.sdc b/flow/designs/gf12/jpeg/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf12/tinyRocket/constraint.sdc b/flow/designs/gf12/tinyRocket/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/aes/constraint.sdc b/flow/designs/gf180/aes/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/ibex/constraint.sdc b/flow/designs/gf180/ibex/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/jpeg/constraint.sdc b/flow/designs/gf180/jpeg/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/riscv32i/constraint.sdc b/flow/designs/gf180/riscv32i/constraint.sdc
@@ -7,6 +7,6 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/uart-blocks/constraint.sdc b/flow/designs/gf180/uart-blocks/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc b/flow/designs/gf180/uart-blocks/uart_rx/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/aes/constraint.sdc b/flow/designs/ihp-sg13g2/aes/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/gcd/constraint.sdc b/flow/designs/ihp-sg13g2/gcd/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/ibex/constraint.sdc b/flow/designs/ihp-sg13g2/ibex/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/jpeg/constraint.sdc b/flow/designs/ihp-sg13g2/jpeg/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/ihp-sg13g2/spi/constraint.sdc b/flow/designs/ihp-sg13g2/spi/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/aes/constraint.sdc b/flow/designs/nangate45/aes/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/gcd/constraint.sdc b/flow/designs/nangate45/gcd/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/ibex/constraint.sdc b/flow/designs/nangate45/ibex/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/jpeg/constraint.sdc b/flow/designs/nangate45/jpeg/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/swerv/constraint.sdc b/flow/designs/nangate45/swerv/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/nangate45/swerv_wrapper/constraint.sdc b/flow/designs/nangate45/swerv_wrapper/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/aes/constraint.sdc b/flow/designs/sky130hd/aes/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/chameleon/constraint.sdc b/flow/designs/sky130hd/chameleon/constraint.sdc
@@ -7,7 +7,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/gcd/constraint.sdc b/flow/designs/sky130hd/gcd/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/ibex/constraint.sdc b/flow/designs/sky130hd/ibex/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hd/jpeg/constraint.sdc b/flow/designs/sky130hd/jpeg/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/aes/constraint.sdc b/flow/designs/sky130hs/aes/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/gcd/constraint.sdc b/flow/designs/sky130hs/gcd/constraint.sdc
@@ -9,7 +9,7 @@ set clk_port [get_ports $clk_port_name]
 
 create_clock -name $clk_name -period $clk_period $clk_port
 
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set non_clock_inputs [all_inputs -no_clocks]
 
 set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
 set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
diff --git a/flow/designs/sky130hs/ibex/constraint.sdc b/flow/designs/sky130hs/ibex/constraint.sdc
diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc
diff --git a/flow/platforms/asap7/constraints.sdc b/flow/platforms/asap7/constraints.sdc
