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Adding a Verilog example using PicoSoC #39
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I think it belongs here. Defining the iopins here is better as well. Let's not add a makefile - it was removed from the others. |
Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile |
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Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go! |
Signed-off-by: gatecat <[email protected]>
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base = os.path.dirname(__file__) | ||
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verilog_sources = [ | ||
f"{base}/picosoc_asic_top.v", | ||
f"{base}/picorv32/picosoc/spimemio.v", | ||
f"{base}/picorv32/picosoc/simpleuart.v", | ||
f"{base}/picorv32/picosoc/picosoc.v", | ||
f"{base}/picorv32/picorv32.v", | ||
] | ||
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for verilog_file in verilog_sources: | ||
with open(verilog_file, 'r') as f: | ||
platform.add_file(verilog_file, f) | ||
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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?
# Clock and reset | ||
i_clk=ClockSignal(), | ||
i_resetn=~ResetSignal(), | ||
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# UART | ||
o_ser_tx=self.uart_0.tx.o, | ||
i_ser_rx=self.uart_0.rx.i, | ||
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# SPI flash | ||
o_flash_csb=self.flash.csn.o, | ||
o_flash_clk=self.flash.clk.o, | ||
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o_flash_io0_oe=self.flash.d.oe[0], | ||
o_flash_io1_oe=self.flash.d.oe[1], | ||
o_flash_io2_oe=self.flash.d.oe[2], | ||
o_flash_io3_oe=self.flash.d.oe[3], | ||
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o_flash_io0_do=self.flash.d.o[0], | ||
o_flash_io1_do=self.flash.d.o[1], | ||
o_flash_io2_do=self.flash.d.o[2], | ||
o_flash_io3_do=self.flash.d.o[3], | ||
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i_flash_io0_di=self.flash.d.i[0], | ||
i_flash_io1_di=self.flash.d.i[1], | ||
i_flash_io2_di=self.flash.d.i[2], | ||
i_flash_io3_di=self.flash.d.i[3], | ||
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# LEDs | ||
o_leds=self.gpio_0.gpio.o |
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Again, might be something worth putting in a toml description?
This is a don't-merge for now, while I figure out while the cxxrtl agent is hitting an
terminating due to uncaught exception of type std::out_of_range: unordered_map::at: key not found
without the workaround added to it...Everything else is ready for review, although I have a couple of questions: