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@gatecat gatecat commented May 14, 2025

This is a don't-merge for now, while I figure out while the cxxrtl agent is hitting an terminating due to uncaught exception of type std::out_of_range: unordered_map::at: key not found without the workaround added to it...

Everything else is ready for review, although I have a couple of questions:

  • should this be in this repo at all, or a different one?
  • should the top level wrapper still use amaranth-orchard pin signatures, as it does now, or is it clearer if it defines the pin signatures in the wrapper too (e.g. as an example for people who want to wrap Verilog with other types of IO)

@gatecat gatecat requested a review from robtaylor May 14, 2025 07:16
@gatecat gatecat force-pushed the add-verilog-example branch 3 times, most recently from b426930 to f9a4d9c Compare May 14, 2025 08:42
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I think it belongs here. Defining the iopins here is better as well.

Let's not add a makefile - it was removed from the others.
Trying to keep things as windows compatible as we can, though still need to test.

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gatecat commented May 14, 2025

Let's not add a makefile - it was removed from the others.

Seems like it wasn't? e.g. https://github.com/ChipFlow/chipflow-examples/blob/main/mcu_soc/Makefile

@gatecat gatecat force-pushed the add-verilog-example branch from f9a4d9c to 7d0876e Compare May 14, 2025 14:44
@gatecat gatecat force-pushed the add-verilog-example branch 3 times, most recently from 91ced06 to 8e2c516 Compare June 23, 2025 07:55
@robtaylor robtaylor force-pushed the add-verilog-example branch 2 times, most recently from 91ced06 to 210cfbd Compare June 23, 2025 07:58
@gatecat gatecat force-pushed the add-verilog-example branch from 210cfbd to e7dde63 Compare July 14, 2025 08:16
@gatecat gatecat marked this pull request as ready for review July 14, 2025 08:16
@gatecat gatecat force-pushed the add-verilog-example branch from e7dde63 to e64bf92 Compare July 14, 2025 08:17
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gatecat commented Jul 14, 2025

Hopefully once ChipFlow/chipflow-lib#129 is in this is ready to go!

@gatecat gatecat force-pushed the add-verilog-example branch from e64bf92 to 90cb442 Compare July 14, 2025 10:13
Comment on lines +50 to +63
base = os.path.dirname(__file__)

verilog_sources = [
f"{base}/picosoc_asic_top.v",
f"{base}/picorv32/picosoc/spimemio.v",
f"{base}/picorv32/picosoc/simpleuart.v",
f"{base}/picorv32/picosoc/picosoc.v",
f"{base}/picorv32/picorv32.v",
]

for verilog_file in verilog_sources:
with open(verilog_file, 'r') as f:
platform.add_file(verilog_file, f)

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Just wondering, could we have a chipflow.toml section to include external code, or maybe use a seperate toml file for defining the import?

Comment on lines +65 to +93
# Clock and reset
i_clk=ClockSignal(),
i_resetn=~ResetSignal(),

# UART
o_ser_tx=self.uart_0.tx.o,
i_ser_rx=self.uart_0.rx.i,

# SPI flash
o_flash_csb=self.flash.csn.o,
o_flash_clk=self.flash.clk.o,

o_flash_io0_oe=self.flash.d.oe[0],
o_flash_io1_oe=self.flash.d.oe[1],
o_flash_io2_oe=self.flash.d.oe[2],
o_flash_io3_oe=self.flash.d.oe[3],

o_flash_io0_do=self.flash.d.o[0],
o_flash_io1_do=self.flash.d.o[1],
o_flash_io2_do=self.flash.d.o[2],
o_flash_io3_do=self.flash.d.o[3],

i_flash_io0_di=self.flash.d.i[0],
i_flash_io1_di=self.flash.d.i[1],
i_flash_io2_di=self.flash.d.i[2],
i_flash_io3_di=self.flash.d.i[3],

# LEDs
o_leds=self.gpio_0.gpio.o
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Again, might be something worth putting in a toml description?

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2 participants