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Adding a Verilog example using PicoSoC
Signed-off-by: gatecat <[email protected]>
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‎.github/workflows/main.yaml

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runs-on: ubuntu-latest
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strategy:
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matrix:
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design: ['mcu_soc', 'minimal']
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design: ['mcu_soc', 'minimal', 'picosoc_verilog']
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steps:
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- name: Check out source code
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uses: actions/checkout@v4
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with:
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submodules: true
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- uses: actions/setup-python@v4
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with:
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runs-on: ubuntu-latest
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strategy:
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matrix:
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design: ['mcu_soc', 'minimal']
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design: ['mcu_soc', 'minimal', 'picosoc_verilog']
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steps:
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- name: Check out source code
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uses: actions/checkout@v4
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with:
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submodules: true
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- name: Set up PDM
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uses: pdm-project/setup-pdm@v4

‎.gitignore

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/build
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/mcu_soc/build
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/minimal/build
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/picosoc_verilog/build
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# testbenches
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*.vcd

‎.gitmodules

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[submodule "picosoc_verilog/design/picorv32"]
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path = picosoc_verilog/design/picorv32
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url = https://github.com/YosysHQ/picorv32

‎picosoc_verilog/README.md

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# PicoSoC (Verilog)
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This example design shows how an existing Verilog design (picosoc) can be wrapped in a minimal layer of Amaranth and submitted to the ChipFlow platform.
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‎picosoc_verilog/chipflow.toml

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[chipflow]
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project_name = "chipflow-examples-picosoc"
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[chipflow.top]
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soc = "design.design:MySoC"
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[chipflow.steps]
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software = "design.steps.software:MySoftwareStep"
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[chipflow.clocks]
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default = 'sys_clk'
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[chipflow.resets]
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default = 'sys_rst_n'
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[chipflow.silicon]
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process = "ihp_sg13g2"
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package = "pga144"
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[chipflow.silicon.pads]
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# System
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sys_clk = { type = "clock", loc = "114" }
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sys_rst_n = { type = "reset", loc = "115" }
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[chipflow.silicon.power]
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dvss0 = { type = "power", loc = "1" }
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dvdd0 = { type = "ground", loc = "9" }
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vss0 = { type = "power", loc = "17" }
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vdd0 = { type = "ground", loc = "25" }
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dvss1 = { type = "power", loc = "33" }
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dvdd1 = { type = "ground", loc = "41" }
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vss1 = { type = "power", loc = "49" }
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vdd1 = { type = "ground", loc = "57" }
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dvss2 = { type = "power", loc = "65" }
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dvdd2 = { type = "ground", loc = "73" }
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vss2 = { type = "power", loc = "81" }
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vdd2 = { type = "ground", loc = "89" }
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dvss3 = { type = "power", loc = "97" }
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dvdd3 = { type = "ground", loc = "105" }
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vss3 = { type = "power", loc = "113" }
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vdd3 = { type = "ground", loc = "121" }
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dvss4 = { type = "power", loc = "129" }
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dvdd4 = { type = "ground", loc = "137" }

‎picosoc_verilog/design/design.py

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import os
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from chipflow_lib.platforms.sim import SimPlatform
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from amaranth import Module, Instance, ClockSignal, ResetSignal
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from amaranth.lib import wiring
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from amaranth.lib.wiring import In, Out, flipped, connect
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from chipflow_lib.platforms import InputIOSignature, OutputIOSignature, BidirIOSignature
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__all__ = ["MySoC"]
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# Define signatures for the top level interface types
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class _QSPISignature(wiring.Signature):
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def __init__(self):
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super().__init__({
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"clk": Out(OutputIOSignature(1)),
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"csn": Out(OutputIOSignature(1)),
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"d": Out(BidirIOSignature(4, all_have_oe=True)),
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})
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class _UARTSignature(wiring.Signature):
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def __init__(self):
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super().__init__({
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"tx": Out(OutputIOSignature(1)),
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"rx": Out(InputIOSignature(1)),
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})
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class _GPIOSignature(wiring.Signature):
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def __init__(self, pin_count=1):
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if pin_count > 32:
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raise ValueError(f"Pin pin_count must be lesser than or equal to 32, not {pin_count}")
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super().__init__({
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"gpio": Out(BidirIOSignature(pin_count, all_have_oe=True))
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})
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class MySoC(wiring.Component):
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def __init__(self):
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# Top level interfaces
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super().__init__({
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"flash": Out(_QSPISignature()),
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"uart_0": Out(_UARTSignature()),
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"gpio_0": Out(_GPIOSignature(pin_count=8)),
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})
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def elaborate(self, platform):
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m = Module()
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base = os.path.dirname(__file__)
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verilog_sources = [
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f"{base}/picosoc_asic_top.v",
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f"{base}/picorv32/picosoc/spimemio.v",
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f"{base}/picorv32/picosoc/simpleuart.v",
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f"{base}/picorv32/picosoc/picosoc.v",
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f"{base}/picorv32/picorv32.v",
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]
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for verilog_file in verilog_sources:
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with open(verilog_file, 'r') as f:
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platform.add_file(verilog_file, f)
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m.submodules.soc = soc = Instance("picosoc_asic_top",
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# Clock and reset
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i_clk=ClockSignal(),
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i_resetn=~ResetSignal(),
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# UART
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o_ser_tx=self.uart_0.tx.o,
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i_ser_rx=self.uart_0.rx.i,
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# SPI flash
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o_flash_csb=self.flash.csn.o,
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o_flash_clk=self.flash.clk.o,
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o_flash_io0_oe=self.flash.d.oe[0],
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o_flash_io1_oe=self.flash.d.oe[1],
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o_flash_io2_oe=self.flash.d.oe[2],
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o_flash_io3_oe=self.flash.d.oe[3],
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o_flash_io0_do=self.flash.d.o[0],
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o_flash_io1_do=self.flash.d.o[1],
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o_flash_io2_do=self.flash.d.o[2],
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o_flash_io3_do=self.flash.d.o[3],
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i_flash_io0_di=self.flash.d.i[0],
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i_flash_io1_di=self.flash.d.i[1],
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i_flash_io2_di=self.flash.d.i[2],
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i_flash_io3_di=self.flash.d.i[3],
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# LEDs
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o_leds=self.gpio_0.gpio.o
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)
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# Hardwire GPIO to output enabled
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m.d.comb += self.gpio_0.gpio.oe.eq(0xFF)
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return m

‎picosoc_verilog/design/picorv32

Submodule picorv32 added at 87c89ac

‎picosoc_verilog/design/picosoc_asic_top.v

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/*
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* PicoSoC - A simple example SoC using PicoRV32
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*
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* Copyright (C) 2017 Claire Xenia Wolf <[email protected]>
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* Copyright (C) 2025 Myrtle Shah <[email protected]>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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`define PICOSOC_MEM picosoc_asic_mem
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module picosoc_asic_top (
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input clk,
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input resetn,
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output ser_tx,
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input ser_rx,
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output [7:0] leds,
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output flash_csb,
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output flash_clk,
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output flash_io0_oe,
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output flash_io1_oe,
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output flash_io2_oe,
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output flash_io3_oe,
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output flash_io0_do,
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output flash_io1_do,
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output flash_io2_do,
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output flash_io3_do,
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input flash_io0_di,
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input flash_io1_di,
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input flash_io2_di,
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input flash_io3_di
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);
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wire iomem_valid;
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reg iomem_ready;
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wire [3:0] iomem_wstrb;
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wire [31:0] iomem_addr;
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wire [31:0] iomem_wdata;
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reg [31:0] iomem_rdata;
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reg [31:0] gpio;
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assign leds = gpio;
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always @(posedge clk) begin
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if (!resetn) begin
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gpio <= 0;
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end else begin
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iomem_ready <= 0;
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if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
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iomem_ready <= 1;
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iomem_rdata <= gpio;
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if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
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if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
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if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
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if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
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end
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end
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end
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picosoc soc (
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.clk (clk ),
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.resetn (resetn ),
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.ser_tx (ser_tx ),
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.ser_rx (ser_rx ),
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.flash_csb (flash_csb ),
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.flash_clk (flash_clk ),
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.flash_io0_oe (flash_io0_oe),
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.flash_io1_oe (flash_io1_oe),
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.flash_io2_oe (flash_io2_oe),
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.flash_io3_oe (flash_io3_oe),
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.flash_io0_do (flash_io0_do),
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.flash_io1_do (flash_io1_do),
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.flash_io2_do (flash_io2_do),
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.flash_io3_do (flash_io3_do),
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.flash_io0_di (flash_io0_di),
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.flash_io1_di (flash_io1_di),
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.flash_io2_di (flash_io2_di),
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.flash_io3_di (flash_io3_di),
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.irq_5 (1'b0 ),
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.irq_6 (1'b0 ),
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.irq_7 (1'b0 ),
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.iomem_valid (iomem_valid ),
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.iomem_ready (iomem_ready ),
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.iomem_wstrb (iomem_wstrb ),
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.iomem_addr (iomem_addr ),
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.iomem_wdata (iomem_wdata ),
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.iomem_rdata (iomem_rdata )
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);
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endmodule
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module picosoc_asic_mem #(
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parameter integer WORDS = 256
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) (
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input clk,
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input [3:0] wen,
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input [21:0] addr,
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input [31:0] wdata,
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output reg [31:0] rdata
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);
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reg [31:0] mem [0:WORDS-1];
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always @(posedge clk) begin
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if (wen == 4'b0)
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rdata <= mem[addr];
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if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
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if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
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if (wen[2]) mem[addr][23:16] <= wdata[23:16];
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if (wen[3]) mem[addr][31:24] <= wdata[31:24];
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end
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endmodule
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‎picosoc_verilog/design/sim/main.cc

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#undef NDEBUG
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#include <cxxrtl/cxxrtl.h>
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#include <cxxrtl/cxxrtl_server.h>
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#include "sim_soc.h"
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#include "models.h"
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#include <fstream>
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#include <filesystem>
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using namespace cxxrtl::time_literals;
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using namespace cxxrtl_design;
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int main(int argc, char **argv) {
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p_sim__top top;
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spiflash_model flash("flash", top.p_io_24_flash__clk_24_o, top.p_io_24_flash__csn_24_o,
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top.p_io_24_flash__d_24_o, top.p_io_24_flash__d_24_oe, top.p_io_24_flash__d_24_i);
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uart_model uart_0("uart_0", top.p_io_24_uart__0__tx_24_o, top.p_io_24_uart__0__rx_24_i);
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gpio_model gpio_0("gpio_0", top.p_io_24_gpio__0__gpio_24_o, top.p_io_24_gpio__0__gpio_24_oe, top.p_io_24_gpio__0__gpio_24_i);
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cxxrtl::agent agent(cxxrtl::spool("spool.bin"), top);
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if (getenv("DEBUG")) // can also be done when a condition is violated, etc
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std::cerr << "Waiting for debugger on " << agent.start_debugging() << std::endl;
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open_event_log(BUILD_DIR "/sim/events.json");
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open_input_commands(PROJECT_ROOT "/design/tests/input.json");
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unsigned timestamp = 0;
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auto tick = [&]() {
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// agent.print(stringf("timestamp %d\n", timestamp), CXXRTL_LOCATION);
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flash.step(timestamp);
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uart_0.step(timestamp);
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gpio_0.step(timestamp);
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top.p_io_24_sys__clk_24_i.set(false);
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agent.step();
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agent.advance(1_us);
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++timestamp;
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top.p_io_24_sys__clk_24_i.set(true);
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agent.step();
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agent.advance(1_us);
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++timestamp;
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// if (timestamp == 10)
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// agent.breakpoint(CXXRTL_LOCATION);
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};
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flash.load_data("../software/software.bin", 0x00100000U);
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agent.step();
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agent.advance(1_us);
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top.p_io_24_sys__rst__n_24_i.set(false);
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tick();
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top.p_io_24_sys__rst__n_24_i.set(true);
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for (int i = 0; i < 1000000; i++)
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tick();
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close_event_log();
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return 0;
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}

‎picosoc_verilog/design/software/.gitignore

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*.o
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*.elf
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*.bin
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generated/

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