Add intrinsics for the new FP conversions introduced by the 2024 dpISA #407
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FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction. 1) Half Precision to 32-bit 2) Half Precision to 64-bit 3) Single Precision to 64-bit 4) Double Precision to 32-bit For the Single Precision to 64-bit and Double Precision to 32-bit variants, this patch adds two new intrinsics, that reduce to - Single Precision to 64-bit : <INST> Dd,Sn - Double Precision to 32-bit : <INST> Sd,Dn The intrinsics for conversions from Half Precision are already defined. However they are documented as reducing to the incorrect instruction format; <INST> Hd,Hn, so this patch fixes them to be - Half Precision to 32-bit : <INST> Sd,Hn - Half Precision to 64-bit : <INST> Dd,Hn
Lukacma
reviewed
Aug 21, 2025
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| `__ARM_FEATURE_FPRCVT` is defined to `1` if there is hardware | ||
| support for floating-point to integer and integer to floating-point | ||
| conversion instructions. This includes the instructions FCVTAS, FCVTAU, FCVTMS, |
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I think this is bit misleading. we have floating point conversions even without this feature. This feature just enables us to do it within SIMD&FP reg file. I would also adjust the header to smth like:
SIMD&FP registers only floating-point conversions extension
or maybe just FPRCVT extension.
Listing all instructions here is also not necessary I think.
| @@ -2590,6 +2600,7 @@ be found in [[BA]](#BA). | |||
| | [`__ARM_FEATURE_FP8DOT2`](#modal-8-bit-floating-point-extensions) | Modal 8-bit floating-point extensions | 1 | | |||
| | [`__ARM_FEATURE_FP8DOT4`](#modal-8-bit-floating-point-extensions) | Modal 8-bit floating-point extensions | 1 | | |||
| | [`__ARM_FEATURE_FP8FMA`](#modal-8-bit-floating-point-extensions) | Modal 8-bit floating-point extensions | 1 | | |||
| | [`__ARM_FEATURE_FPRCVT`](#floating-point-to-from-integer-conversion-intrinsics) | Floating-point to/from integer conversion intrinsics | 1 | | |||
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Same as above. This description is bit misleading in my opinioon.
| @@ -4083,35 +4103,35 @@ float16_t vcvth_f16_u16(uint16_t a) a -> Hn UCVTF Hd,Hn Hd -> result A64 | |||
| float16_t vcvth_f16_u32(uint32_t a) a -> Hn UCVTF Hd,Hn Hd -> result A32/A64 | |||
| float16_t vcvth_f16_u64(uint64_t a) a -> Hn UCVTF Hd,Hn Hd -> result A64 | |||
| int16_t vcvth_s16_f16(float16_t a) a -> Hn FCVTZS Hd,Hn Hd -> result A64 | |||
| int32_t vcvth_s32_f16(float16_t a) a -> Hn FCVTZS Hd,Hn Hd -> result A32/A64 | |||
| int64_t vcvth_s64_f16(float16_t a) a -> Hn FCVTZS Hd,Hn Hd -> result A64 | |||
| int32_t vcvth_s32_f16(float16_t a) a -> Hn FCVTZS Sd,Hn Sd -> result A32/A64 | |||
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I am not usre if A32 should stay here. I think these instructions are A64 only but I might be wrong
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FEAT_FPRCVT adds 4 new variants for each FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, FCVTPU, FCVTZS, and FCVTZU instruction. 1) Half Precision to 32-bit
2) Half Precision to 64-bit
3) Single Precision to 64-bit
4) Double Precision to 32-bit
For the Single Precision to 64-bit and Double Precision to 32-bit variants, this patch adds two new intrinsics, that reduce to
The intrinsics for conversions from Half Precision are already defined. However they are documented as reducing to the incorrect instruction format; Hd,Hn, so this patch fixes them to be
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