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@AlexPoupakis AlexPoupakis commented Jul 18, 2025

This PR provides everything necessary to make the parallel router deterministic without having to offset the lookahead costs.

  • Added floating point tolerance to the post target pruning condition
    Note: the vtr::isclose() function cannot used because it checks the absolute difference (it is symmetric), whereas we can only tolerate error on the left hand side (assymetric). Using this function makes the parallel router non-deterministic!
  • Created SIMPLE lookahead which can only load (not compute) a cost map and query it based on distance.

By using appropriate (admissible) cost maps, both of these changes allow the parallel router to be deterministic. Attached are admissible cost maps for the flagship VTR architecture (k6_frac_N10_frac_chain_mem32K_40nm) devices.
vtr_devices_admissible_lookahead_maps.zip

… from memory and queries it using distances. If the cost map contains the minimum delay and minimum congestion costs per distance, then the lookahead is admissible.
… for floating point errors. If the lookahead is admissible and we account for the floating point arithmetic errors, the parallel router is deterministic.
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Jul 18, 2025
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Hi Alex,

Thank you very much for raising this PR! I am very excited to try this out. I left some comments, and once resolved I think this will be good to merge.

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AlexandreSinger commented Jul 20, 2025

There are also some minor formatting issues:

https://github.com/verilog-to-routing/vtr-verilog-to-routing/actions/runs/16373929193/job/46342261017?pr=3203

You can run make format from the root directory or just fix them by hand.

@github-actions github-actions bot added the docs Documentation label Jul 22, 2025
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LGTM

@AlexandreSinger AlexandreSinger merged commit 246053d into verilog-to-routing:master Aug 20, 2025
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