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WIP: Subtraction Fix in ODIN

lang-cppC/C++ codeC/C++ code

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

Parmys

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2307

#2307 In verilog-to-routing/vtr-verilog-to-routing;

· navidjafarof opened on May 8, 2023

Upgrade the Yosys+Odin-II Front-end

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

Yosys+Odin-IIThe Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flowThe Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2148

#2148 In verilog-to-routing/vtr-verilog-to-routing;

· sdamghan opened on Aug 29, 2022

[WIP] Tileable Routing Resource Graph Builder

buildBuild systemBuild system

docsDocumentationDocumentation

external_libs

infraProject InfrastructureProject Infrastructure

lang-cppC/C++ codeC/C++ code

lang-hdlHardware Description Language (Verilog/VHDL)Hardware Description Language (Verilog/VHDL)

lang-makeCMake/Make codeCMake/Make code

lang-netlist

lang-pythonPython codePython code

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

liblog

libpugiutil

libvtrutil

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

Parmys

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2135

#2135 In verilog-to-routing/vtr-verilog-to-routing;

· tangxifan opened on Aug 16, 2022

Support for simple dual port RAMs in ODIN/ODIN+Yosys

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

Yosys+Odin-IIThe Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flowThe Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow

Status: Open.

#2123 In verilog-to-routing/vtr-verilog-to-routing;

· aman26kbm opened on Aug 11, 2022

WIP: clang-tidy fixes around const std::string references.

ABCABC Logic Optimization & Technology Mapping ToolABC Logic Optimization & Technology Mapping Tool

external_libs

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libpugiutil

libvtrutil

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1764

#1764 In verilog-to-routing/vtr-verilog-to-routing;

· mithro opened on Jun 3, 2021

Enabled BLIF buffer elimination in preparation for InOuts

lang-cppC/C++ codeC/C++ code

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

tests

VTR FlowVTR Design Flow (scripts/benchmarks/architectures)VTR Design Flow (scripts/benchmarks/architectures)

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1520

#1520 In verilog-to-routing/vtr-verilog-to-routing;

· djns99 opened on Sep 1, 2020

WIP: Implement inout support into ODIN II

lang-cppC/C++ codeC/C++ code

lang-hdlHardware Description Language (Verilog/VHDL)Hardware Description Language (Verilog/VHDL)

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

tests

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1292

#1292 In verilog-to-routing/vtr-verilog-to-routing;

· djns99 opened on May 1, 2020