Support for simple dual port RAMs in ODIN/ODIN+Yosys

[aman26kbm]

Moving from email to GitHub feature request.

Proposed Behaviour

Provide support for simple dual port (SDP) RAMs in ODIN/ODIN+Yosys

Current Behaviour

Currently, only single port (SP) and true dual port (TDP) RAMs are supported:

 
 *                                              en2                         *                                                             
 *                                    en1      |                            *                                           en                                
 *                       CLK       |          |                            *                     CLK                 |                                   
 *                      __|_____|_____|___                      *                      __|_________|_____                          
 *                     |                  |                      *                     |                                 |                         
 *                     |                  |                      *                     |                                 |                          
 *     data1 --->|                  | <--- addr1     *                     |                                 |                         
 *                     |          DPRAM     |                      *        data --->|          SPRAM          |<--- addr              
 *     data2 --->|                                |<--- addr2      *                      |                                 |                         
 *                     |                                |                      *                     |                                  |                         
 *                     |________________|                      *                     |_________________|                         
 *                              |            |                                 *                                        |                                   
 *                              |            |                                 *                                        |                                   
 *                              v           v                                *                                        v                                    
 *                           out1        out2                           *                                       out                                  
        

Possible Solution

Context

This is not needed right now. This is for the future. Adding Dr. Kenneth Kent to assign it to a future student.

[mithro]

FYI - Yosys recently went through a pretty big refactor to support more types of memory styles. See the work from
@mwkmwkmwk - https://github.com/YosysHQ/yosys/pulls?q=author%3Amwkmwkmwk+

[sdamghan]

@poname - considering the Yosys recent changes on memory blocks, you would be required to consider upstreaming the VTR-Yosys for Odintechmap and provide the support for newly added components, as well. This could be postponed to the second phase of your development as we expect Odintechmap initially work fine with the old version of Yosys added to the VTR repository.
Adding @vaughnbetz on this thread as he already requested for upstreaming VTR-Yosys.

[github-actions]

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[vaughnbetz]

Not sure if the move to yosys + parmys has resolved this, but sending to Logan to check once he has time. @loglav03 : let me know if you need more info on this. I suggest trying a test case once you have the latest yosys going, to see if we use simple dual port RAMs (one read, one write port) when we can, instead of using true dual port (two R/W ports).

[loglav03]

@vaughnbetz - Now that the latest Yosys is working with vtr, I'm ready to start testing this out. I'm not to sure what commands I should be using for this (circuit and architecture) and I'm assuming I should be looking at some pre-vpr output file

[vaughnbetz]

@aman26kbm : do you have an arch file with simple dual port RAMs in it? I took a quick look and didn't see one with this feature, which may make sense as we didn't support simple dual port RAMs.

Here's my attempt to write a simple dual port RAM model. I haven't made the clustered block (BRAM) that would correspond to this; I don't think that would be needed for yosys+parmys but I'm not sure.

We would want yosys + parmys to write out instances of these models in the pre-vpr.blif file.

<model name="simple_dual_port_ram">
  <input_ports>
    <port name="we" clock="clk"/> <!-- write enable -->
    <port name="addr_read" clock="clk"/> <!-- address lines -->
    <port name="addr_write" clock="clk"/> <!-- address lines -->
    <port name="data_in" clock="clk"/>  <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
    <port name="clk" is_clock="1"/> <!-- memories are often clocked -->
  </input_ports>
  <output_ports>
    <port name="out" clock="clk"/>   <!-- output can be broken down into smaller bit widths minimum size 1 -->
  </output_ports>
</model>

[aman26kbm]

Yeah I don't think we have an arch file with simple dual port RAMs. Vaughn's model looks good.

In the pb_type, we have something called port_class. For single port, we have:

      <input name="addr" num_pins="14" port_class="address"/>
      <input name="data" num_pins="2" port_class="data_in"/>
      <input name="we" num_pins="1" port_class="write_en"/>
      <output name="out" num_pins="2" port_class="data_out"/>
      <clock name="clk" num_pins="1" port_class="clock"/>

And for true dual port, we say:

      <input name="addr1" num_pins="10" port_class="address1"/>
      <input name="addr2" num_pins="10" port_class="address2"/>
      <input name="data1" num_pins="32" port_class="data_in1"/>
      <input name="data2" num_pins="32" port_class="data_in2"/>
      <input name="we1" num_pins="1" port_class="write_en1"/>
      <input name="we2" num_pins="1" port_class="write_en2"/>
      <output name="out1" num_pins="32" port_class="data_out1"/>
      <output name="out2" num_pins="32" port_class="data_out2"/>
      <clock name="clk" num_pins="1" port_class="clock"/> 

I don't know where the port class is used, but we will need to have address1, address2 and then data_in and data_out for simple dual port RAM.