Skip to content
Open
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion src/main/scala/Bits.scala
Original file line number Diff line number Diff line change
Expand Up @@ -98,8 +98,9 @@ abstract class Bits extends Data with proc {
}
override def assign(src: Node): Unit = {
checkAssign(src)
if (Module.current.hasWhenCond) ChiselError.error({"cannot conditionally assign to Wire " + this + " RHS: " + src});
if (inputs.isEmpty) inputs += src
else ChiselError.error({"reassignment to Wire " + this + " with inputs " + this.inputs(0) + " RHS: " + src});
else inputs.update(0, src)
}

override def procAssign(src: Node): Unit = {
Expand Down