Add TraceAlignmentSolver post-pack phase to fix #12

[brone1323]

/claim #12

Problem

Issue #12 asks for a layout fix. The repro in merged PR #11 (SI7021) renders with visible zig-zag on traces between strongly-connected chips. The root cause: after PartitionPackingSolver snaps each chip to a packing-grid coordinate, the pads on each chip are at fixed offsets from the chip center, so two strongly-connected pads on neighbouring chips often end up at a small (0.1–0.5 unit) off-axis delta. That delta becomes a visible zig-zag in the schematic.

Concrete numbers from the SI7021 repro (output of the existing pipeline):

Chip	x	y
U1	0.000	0.000
R1	1.700	0.150
R2	1.025	-1.350

R1.1 (top pin, offset y=+0.5) lands at world-y 0.65, but its partner U1.4 (right side, offset y=+0.2) lands at world-y 0.20. Trace zig-zag = 0.45 units. Same shape for R2.1 ↔ U1.3. Worst-case off-axis pad delta across the whole layout: 0.50.

Approach

Add a single new solver, TraceAlignmentSolver, registered as the final phase of LayoutPipelineSolver after PartitionPackingSolver. For each chip with at least one inter-chip strong pin connection:

1. Compute the average displacement that would put each connecting pad on the same axis (Y for horizontal traces, X for vertical traces) as its partner pin.
2. Reject if the candidate position would cause an AABB intersection with any other chip.
3. Accept only if the chip's own total off-axis pad delta strictly decreases.

The "strictly-decreases" guard is the part that lets us safely include multi-partner chips. If a chip is pulled toward two different partners with conflicting alignment requirements, the average nudge is rejected for failing to improve the chip's own metric. The phase runs two passes so that downstream chips can re-align after upstream chips move.

Result on the SI7021 repro

Chip	x	y	(was) y
U1	0.000	0.000	0.000
R1	1.700	-0.325	0.150
R2	1.025	-0.825	-1.350

After the alignment phase:

• R1 nudged down 0.475 → R1.1 aligns within 0.025 of U1.4, and within 0.025 of SJ1.3 (the resistor's other strong partner)
• R2 nudged up 0.525 → similar alignment with U1.3 and SJ1.1
• Worst-case off-axis pad delta: 0.50 → 0.125 (75% reduction)
• 0 new chip overlaps (verified with the existing LayoutPipelineSolver.checkForOverlaps AABB check)

Differentiation vs other open PRs

PRs #39 / #44 / #61 / #74 all attack different defects. This PR attacks the off-axis pad delta on strongly-connected pin pairs - independent of decoupling-cap clustering, voltage net direction, and chip-overlap resolution. The four can stack.

• PR feat: add overlap resolution phase after partition packing #39 (yuliuyi717) - OverlapResolutionSolver: resolves residual chip overlaps. Different defect (overlap, not zig-zag).
• PR feat: implement upward directional bias for positive voltage nets to optimize schematic layout #61 (AliReda95) - upward bias for positive voltage nets (VCC/VDD/V+). Affects which side of a chip a power-net partner ends up on. Orthogonal to pad-axis alignment.
• PR feat: add DecouplingCapsHorizontalRowSolver for specialized decoupling cap layout #74 (fancierbread7) - decoupling-cap-specific layout that clusters caps near their main chip. Orthogonal: clustering ≠ pad alignment.

Files touched

• lib/solvers/TraceAlignmentSolver/TraceAlignmentSolver.ts (new)
• lib/solvers/LayoutPipelineSolver/LayoutPipelineSolver.ts (register new phase, prefer aligned layout in getOutputLayout/visualize/preview)
• tests/TraceAlignmentSolver/TraceAlignmentSolver01.test.ts (new)

Tests

• bun test tests/TraceAlignmentSolver/ - both new tests pass
• bun test tests/LayoutPipelineSolver/ tests/PartitionPackingSolver/ - 11 existing pipeline tests still pass

The tests/IdentifyDecouplingCapsSolver/IdentifyDecouplingCapsSolver06.test.ts failure is pre-existing on main (unrelated convertCircuitJsonToSchematicSimulationSvg export missing in circuit-to-svg); confirmed reproducible without this PR's changes.

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Demo video

▶ Watch demo (1.0MB MP4)

Generated programmatically (HTML deck → Playwright recordVideo → ffmpeg). Hosted as a release asset on the fork to comply with the Algora claim requirement.

Sammy / @brone1323