feat: specialized linear layout for decoupling capacitor partitions

[chengyixu]

/claim #15

Summary

• Bypass PackSolver2 for decoupling cap partitions: When SingleInnerPartitionPackingSolver encounters a partition with partitionType === "decoupling_caps", it skips the general packing algorithm and uses a new createLinearDecouplingCapLayout() method instead
• Clean horizontal row layout: Decoupling capacitors are arranged in a single horizontal line, sorted by chipId for deterministic ordering, with consistent spacing using decouplingCapsGap (falls back to chipGap)
• Centered at origin: The row is centered at x=0, y=0 so it integrates cleanly with the partition packing phase

Changes

lib/solvers/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.ts

• Added early return in _step() for decoupling_caps partition type
• Added createLinearDecouplingCapLayout() private method that places caps in a clean horizontal row

tests/PackInnerPartitionsSolver/LinearDecouplingCapLayout.test.ts

• 5 new tests covering:
  • Linear row layout with correct Y-alignment and gap spacing
  • Full pipeline integration
  • Centering around origin
  • Deterministic ordering (sorted by chipId)
  • Non-decoupling partitions still use PackSolver2

Why this works

The existing pipeline already identifies decoupling caps (IdentifyDecouplingCapsSolver) and creates separate partitions for them (ChipPartitionsSolver with partitionType: "decoupling_caps"). The problem was that PackSolver2 produces messy, overlapping layouts for groups of identically-sized 2-pin components. This PR adds a targeted override: when a partition is known to contain only decoupling caps, arrange them in a clean row instead.

Zero impact on non-decoupling partitions — the early return only fires for tagged partitions.

Test plan

• All 5 new tests pass (bun test tests/PackInnerPartitionsSolver/LinearDecouplingCapLayout.test.ts)
• All existing tests pass (22 pass, 1 skip; the 1 pre-existing error in IdentifyDecouplingCapsSolver06.test.ts is a dependency issue on main)
• Formatting passes (bun run format:check)

[vercel]

@chengyixu is attempting to deploy a commit to the tscircuit Team on Vercel.

A member of the Team first needs to authorize it.

[chengyixu]

Hi @seveibar — gentle ping on this PR. This adds specialized linear layout for decoupling capacitor partitions. All CI checks are passing. Happy to address any feedback or questions!

[chengyixu]

Friendly ping @seveibar -- this PR has been open for 40 days with all tests/checks green. It adds specialized linear layout for decoupling capacitor partitions. The Vercel failure appears to be an auth redirect. Let me know if anything else is needed! Thanks.

[chengyixu]

Hi @seveibar — gentle ping on this PR (open ~40 days). All core CI checks pass (test ✅, format-check ✅, type-check ✅). The Vercel status shows 'needs authorization' which requires a maintainer action. Happy to address any feedback when you get a chance!