feat: reset ESP32-S2 via RTC watchdog on USB-OTG (DTR/RTS latch is a no-op there)#45
Open
jgangemi wants to merge 1 commit into
Open
feat: reset ESP32-S2 via RTC watchdog on USB-OTG (DTR/RTS latch is a no-op there)#45jgangemi wants to merge 1 commit into
jgangemi wants to merge 1 commit into
Conversation
…no-op there) - distinguish native USB-OTG (ESP32-S2, no USB-Serial-JTAG bridge) from USB-Serial-JTAG (S3/C3/C6/H2/C5) via a new chipDef.HardResetOTG hook, instead of conflating both under usesUSB - add esp32s2HardReset/esp32s2WatchdogReset mirroring esptool's ESP32S2ROM.hard_reset()/watchdog_reset(): gate on GPIO_STRAP_REG and RTC_CNTL_OPTION1_REG, then arm the RTC WDT (unlock, set timeout, enable stage-0 system reset, relock) instead of toggling DTR/RTS - falls back to the existing hardResetUSB DTR/RTS path when the gate indicates a watchdog reset wouldn't reliably exit download mode, or when the gate registers are unreadable (e.g. secure download mode) - preserves all existing behavior for S3/C3/C6/H2/C5 (HardResetOTG is nil for those chipDefs) and the non-USB path
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
USB-Serial-JTAG (S3/C3/C6/H2/C5) via a new chipDef.HardResetOTG hook,
instead of conflating both under usesUSB
ESP32S2ROM.hard_reset()/watchdog_reset(): gate on GPIO_STRAP_REG and
RTC_CNTL_OPTION1_REG, then arm the RTC WDT (unlock, set timeout,
enable stage-0 system reset, relock) instead of toggling DTR/RTS
indicates a watchdog reset wouldn't reliably exit download mode, or
when the gate registers are unreadable (e.g. secure download mode)
nil for those chipDefs) and the non-USB path