Accelerator overhaul #101
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Accelerator overhaul #101
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…ation of load/compute/store and use of HLS streams Fix a misplaced cast from score_t to input_t. Remove the now-unused copy_input and copy_output methods
… Move to pyproject.toml for main conifer. Use conifer_xrt_runtime package in the conifer HLS backend driver
…se HLS and FPU runtimes
…ivers to separate files with optional loading. Provide lightweight Python wrappers to C++ XRT classes for utility
Include hls_stream header from Vitis HLS Add ap_types submodule
…date the logic of finding which headers to use based on the externals Tidy up hls_stream include, and remove setup of JSON and ap_types headers from CI before_script Make sure submodules are cloned in CI
Source the XRT environment in the XRT build test Add git to the XRT test setup Clone the submodules in the conifer-xrt CI
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Overview
This PR overhauls the support for building accelerators from conifer models. There are two main aspects:
XRT drivers
Since its
v3.1release,pynqis deprecating support for Alveo platforms. I explored XRT's provided Python bindings viapyxrt, and made some working implementations. However, it doesn't expose XRT's API for reading and writing registers. This functionality is quite useful for the quality-of-life features of the drivers, in that the IPs produced withconifercontain some high level information about the IP which needs to be retrieved via registers. For that reason this PR provides a native XRT C++ driver implementation, with Python bindings viapybind11. Happily, this also turns out to be marginally faster thanpyxrt.These drivers are split into a standalone package within the repo named
conifer-xrt. This enables installing the package viapip, without introducing a dependency on XRT installation for all ofconifer. XRT needs to be manually installed by users via AMD/Xilinx, and is only relevant for these accelerators designs.I also add the nlohmann JSON library as a submodule, since the
conifer-xrtpackage needs to build against it at installation time. In a follow up PR I plan to make use of that for the C++ backend, relating to #87.This PR solves #99 (in spirit)
load/compute/store
This part relates to the Xilinx HLS backend top-level wrapper, which has been refactored to properly partition the load, compute, and store tasks along with AMD/Xilinx guidelines. I've written up the implementation and observations, but the main plot is here:
Some attempts at this approach for the FPU backend only slowed things down, so I plan to come back to that.