Circuit Elements

In PyHCL, we use several circuit elements to define the behavior of the circuit. Circuit elements are the major componenet of a module. They define the logic and state behavior of the circuit. In this section, we would introduce some commonly used circuit elements include wire, register, and memory. These three circuit elements could construct almost all circuits.

Wire

Wire is the a circuit element act as wire in Verilog, for constructing a hardware wire. It preforms a wire connection for other elements operations. Wire cannot store any statement, users could treat it as a node in circuit or in FIRRTL syntax tree. We could define a Wire like this:

w = Wire(<cdatatype>)

For example, we want to define a Wire as the node of the addition operation of two circuit elements:

w <<= io.a + io.cin
io.b <<= w	# Connect w to output port b

Under certian circumstances, we could implement the same circuit logic without using Wire:

w = io.a + io.cin
io.b <<= w	# The same as the example above

Register

Register is the basic elements in the circuit. Register is state elements, and it is the most important part in sequential circuit. We provide two APIs to define a register:

r1 = Reg(<cdatatype>)			# Register definition without initial value
r2 = RegInit(<cdatatype>)		# Register definition with inital value

The difference between Reg and RegInit is the compile Verilog code. Using Reg, the register would not have reset value:

always @(posedge clock) begin
    r <= _T[15:0];
end

Using RegInit, the register will set to the initial value when reset signal reach positive edge:

always @(posedge clock) begin
    if (reset) begin
      r <= 16'h0;
    end else begin
      r <= _T[15:0];
    end
end

We give a example of using register:

count = RegInit(U.w(16)(0))
count <<= count + U(1)

To be noticed that, all operations on a register is based on the clock. count register would increase 1 in every positive edge. In PyHCL, the statement such as always in Verilog doesn't exist. We would introduce how to write sequential circuits in PyHCL in section 8.

Registers support all built-in PyHCL operations, we give a example of extracting bit field of register:

lower_bits <<= count[7:0]

Memory

PyHCL only support combinational/asynchronous-read, sequential/synchronous-write memories using register array. Since that lots of memories of different FPGA manufacturer would provide thier own ip cores for memories. We suggest using the blackbox feature of PyHCL to use memories on devices. The blackbox feature will introduce in advanced features in section 9.

We could define a memory similar to the Vec datatype:

m = Mem(<size>, <cdatatype>)

size is the length of the memory, and cdatatype is the datatype of the memory, only support basic types. The PyHCL built-in memory is a register array:

m = Mem(4, U.w(16))

Which would compile to Verilog code:

reg [15:0] m [0:3];

To indexing the specific element in memory, we use [] operator to do so. To be noticed, the index must be PyHCL literal unsigned integer:

m[U(0)] <<= U(1)	# Entry 0 becomes unsigned integer value 1

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