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Merged
merged 3 commits into from
Oct 5, 2025
Merged

Dev #85

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1d02dd0
feat: add elem num output port for async fifo
maksyuki Oct 5, 2025
d546974
feat: add dma i2s hw trg impl
maksyuki Oct 5, 2025
ec0a292
feat: add lower and upper bound for i2s tx fifo
maksyuki Oct 5, 2025
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18 changes: 11 additions & 7 deletions crt/inc/firmware.h
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Original file line number Diff line number Diff line change
Expand Up @@ -78,9 +78,11 @@
#define reg_i2c0_status (*(volatile uint32_t*)0x1000601C)
// i2s
#define reg_i2s_mode (*(volatile uint32_t*)0x10007000)
#define reg_i2s_txdata (*(volatile uint32_t*)0x10007004)
#define reg_i2s_rxdata (*(volatile uint32_t*)0x10007008)
#define reg_i2s_status (*(volatile uint32_t*)0x1000700C)
#define reg_i2s_upbound (*(volatile uint32_t*)0x10007004)
#define reg_i2s_lowbound (*(volatile uint32_t*)0x10007008)
#define reg_i2s_txdata (*(volatile uint32_t*)0x1000700C)
#define reg_i2s_rxdata (*(volatile uint32_t*)0x10007010)
#define reg_i2s_status (*(volatile uint32_t*)0x10007014)
// 1-wire
#define reg_onewire_clkdiv (*(volatile uint32_t*)0x10008000)
#define reg_onewire_zerocnt (*(volatile uint32_t*)0x10008004)
Expand All @@ -92,10 +94,12 @@
// dma(32b xfer, hardware trigger by I2S fifo, QSPI fifo)
#define reg_dma_mode (*(volatile uint32_t*)0x10009000)
#define reg_dma_srcaddr (*(volatile uint32_t*)0x10009004)
#define reg_dma_dstaddr (*(volatile uint32_t*)0x10009008)
#define reg_dma_xferlen (*(volatile uint32_t*)0x1000900C)
#define reg_dma_start (*(volatile uint32_t*)0x10009010)
#define reg_dma_status (*(volatile uint32_t*)0x10009014)
#define reg_dma_srcincr (*(volatile uint32_t*)0x10009008)
#define reg_dma_dstaddr (*(volatile uint32_t*)0x1000900C)
#define reg_dma_dstincr (*(volatile uint32_t*)0x10009010)
#define reg_dma_xferlen (*(volatile uint32_t*)0x10009014)
#define reg_dma_start (*(volatile uint32_t*)0x10009018)
#define reg_dma_status (*(volatile uint32_t*)0x1000901C)
// sys ctrl
#define reg_sysctrl_coresel (*(volatile uint32_t*)0x1000A000)
#define reg_sysctrl_ipsel (*(volatile uint32_t*)0x1000A004)
Expand Down
4 changes: 2 additions & 2 deletions crt/src/firmware.c
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Original file line number Diff line number Diff line change
Expand Up @@ -175,8 +175,8 @@ void main()
// ip_1wire_test();
// ip_spisd_read((uint32_t)0x51004000, (uint32_t)44);
// ip_spisd_test();
ip_i2s_test();
// ip_dma_test();
// ip_i2s_test();
ip_dma_test();
// wav_file_decoder((uint32_t)0x51004000);
// wav_file_decoder((uint32_t)0x54737000);

Expand Down
13 changes: 10 additions & 3 deletions crt/src/tinydma.c
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Original file line number Diff line number Diff line change
Expand Up @@ -6,11 +6,18 @@
void ip_dma_test() {
printf("dma test\n");

// reg_dma_srcaddr = (uint32_t)0x51004000;
// i2s
reg_i2s_mode = (uint32_t)1;
reg_i2s_upbound = (uint32_t)120;
reg_i2s_lowbound = (uint32_t)32;
// dma
reg_dma_mode = (uint32_t)1;
// reg_dma_srcaddr = (uint32_t)0x51004000;
reg_dma_srcaddr = (uint32_t)0x40000000;
reg_dma_dstaddr = (uint32_t)0x10007004;
reg_dma_xferlen = (uint32_t)256;
reg_dma_srcincr = (uint32_t)1;
reg_dma_dstaddr = (uint32_t)0x1000700C;
reg_dma_dstincr = (uint32_t)0;
reg_dma_xferlen = (uint32_t)512;
reg_dma_start = (uint32_t)1;

while(reg_dma_status & 1);
Expand Down
6 changes: 4 additions & 2 deletions crt/src/tinyi2s.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2,14 +2,16 @@
#include <tinyprintf.h>
#include <tinyi2s.h>

uint32_t test_data[] = {0x12345678, 0x12345679, 0x1234567A};
uint32_t test_data[] = {0x12345678, 0x12345679, 0x1234567A, 0x2345EF23, 0x2345EF24, 0x2345EF25};

void ip_i2s_test() {
// fifo wr mode
printf("i2s test\n");
reg_i2s_mode = (uint32_t)1;
reg_i2s_upbound = (uint32_t)120;
reg_i2s_lowbound = (uint32_t)32;

for(uint32_t i = 0; i < 3; ++i) {
for(uint32_t i = 0; i < 6; ++i) {
// while(reg_i2s_status & (uint32_t)1); // check if fifo is full or not
reg_i2s_txdata = test_data[i];
}
Expand Down
13 changes: 12 additions & 1 deletion rtl/ip/native/async_fifo.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,8 @@ module async_fifo #(
input logic rd_rst_n_i,
input logic rd_en_i,
output logic [DATA_WIDTH-1:0] rd_data_o,
output logic rd_empty_o
output logic rd_empty_o,
output logic [ DEPTH_POWER:0] elem_num_o
);

localparam int FIFO_DEPTH = 2 ** DEPTH_POWER;
Expand All @@ -32,6 +33,7 @@ module async_fifo #(
logic [PTR_WIDTH-1:0] r_wr_ptr_gray, r_rd_ptr_gray;
logic [PTR_WIDTH-1:0] r_wr_ptr_gray_sync[0:1];
logic [PTR_WIDTH-1:0] r_rd_ptr_gray_sync[0:1];
logic [PTR_WIDTH-1:0] s_rd_ptr_bin_sync;

// wr logic
always_ff @(posedge wr_clk_i or negedge wr_rst_n_i) begin
Expand Down Expand Up @@ -84,10 +86,19 @@ module async_fifo #(

assign rd_empty_o = r_rd_ptr_gray == r_wr_ptr_gray_sync[1];

assign elem_num_o = r_wr_ptr_bin - s_rd_ptr_bin_sync;

function automatic logic [PTR_WIDTH-1:0] bin2gray(input logic [PTR_WIDTH-1:0] bin);
return (bin >> 1) ^ bin;
endfunction

gray2bin #(
.DATA_WIDTH(PTR_WIDTH)
) u_gray2bin (
.gray_i(r_rd_ptr_gray_sync[1]),
.bin_o (s_rd_ptr_bin_sync)
);

initial begin
if (DEPTH_POWER < 1 || DEPTH_POWER > 10) $error("DEPTH_POWER ERROR");
if (DATA_WIDTH < 1 || DATA_WIDTH > 256) $error("DATA_WIDTH ERROR");
Expand Down
67 changes: 51 additions & 16 deletions rtl/ip/native/dma.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -14,10 +14,12 @@
// verilog_format: off
`define NATV_DMA_MODE 8'h00
`define NATV_DMA_SRCADDR 8'h04
`define NATV_DMA_DSTADDR 8'h08
`define NATV_DMA_XFERLEN 8'h0C
`define NATV_DMA_START 8'h10
`define NATV_DMA_STATUS 8'h14
`define NATV_DMA_SRCINCR 8'h08
`define NATV_DMA_DSTADDR 8'h0C
`define NATV_DMA_DSTINCR 8'h10
`define NATV_DMA_XFERLEN 8'h14
`define NATV_DMA_START 8'h18
`define NATV_DMA_STATUS 8'h1C
// verilog_format: on

`endif
Expand All @@ -26,6 +28,7 @@ module nmi_dma (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic i2s_tx_proc_i,
nmi_if.slave nmi,
nmi_if.master nmi_dma
// verilog_format: on
Expand All @@ -37,11 +40,15 @@ module nmi_dma (
logic [31:0] s_nmi_rdata_d, s_nmi_rdata_q;

logic s_dma_mode_en;
logic s_dma_mode_d, s_dma_mode_q;
logic [1:0] s_dma_mode_d, s_dma_mode_q;
logic s_dma_srcaddr_en;
logic [31:0] s_dma_srcaddr_d, s_dma_srcaddr_q;
logic s_dma_srcincr_en;
logic s_dma_srcincr_d, s_dma_srcincr_q;
logic s_dma_dstaddr_en;
logic [31:0] s_dma_dstaddr_d, s_dma_dstaddr_q;
logic s_dma_dstincr_en;
logic s_dma_dstincr_d, s_dma_dstincr_q;
logic s_dma_xferlen_en;
logic [31:0] s_dma_xferlen_d, s_dma_xferlen_q;
logic s_dma_status_d, s_dma_status_q;
Expand All @@ -55,9 +62,10 @@ module nmi_dma (
assign nmi.rdata = s_nmi_rdata_q;


// [3]: resv [2]: spi fifo trg [1]: i2s fifo trg [0]: sft trg
assign s_dma_mode_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_MODE;
assign s_dma_mode_d = nmi.wdata[0];
dffer #(1) u_dma_mode_dffer (
assign s_dma_mode_d = nmi.wdata[1:0];
dffer #(2) u_dma_mode_dffer (
clk_i,
rst_n_i,
s_dma_mode_en,
Expand All @@ -83,6 +91,17 @@ module nmi_dma (
);


assign s_dma_srcincr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_SRCINCR;
assign s_dma_srcincr_d = nmi.wdata[0];
dffer #(1) u_dma_srcincr_dffer (
clk_i,
rst_n_i,
s_dma_srcincr_en,
s_dma_srcincr_d,
s_dma_srcincr_q
);


assign s_dma_dstaddr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_DSTADDR;
always_comb begin
s_dma_dstaddr_d = s_dma_dstaddr_q;
Expand All @@ -99,6 +118,16 @@ module nmi_dma (
s_dma_dstaddr_q
);

assign s_dma_dstincr_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_DSTINCR;
assign s_dma_dstincr_d = nmi.wdata[0];
dffer #(1) u_dma_dstincr_dffer (
clk_i,
rst_n_i,
s_dma_dstincr_en,
s_dma_dstincr_d,
s_dma_dstincr_q
);

assign s_dma_xferlen_en = s_nmi_wr_hdshk && nmi.addr[7:0] == `NATV_DMA_XFERLEN;
always_comb begin
s_dma_xferlen_d = s_dma_xferlen_q;
Expand Down Expand Up @@ -146,9 +175,11 @@ module nmi_dma (
always_comb begin
s_nmi_rdata_d = s_nmi_rdata_q;
unique case (nmi.addr[7:0])
`NATV_DMA_MODE: s_nmi_rdata_d = {31'd0, s_dma_mode_q};
`NATV_DMA_MODE: s_nmi_rdata_d = {30'd0, s_dma_mode_q};
`NATV_DMA_SRCADDR: s_nmi_rdata_d = s_dma_srcaddr_q;
`NATV_DMA_SRCINCR: s_nmi_rdata_d = {31'd0, s_dma_srcincr_q};
`NATV_DMA_DSTADDR: s_nmi_rdata_d = s_dma_dstaddr_q;
`NATV_DMA_DSTINCR: s_nmi_rdata_d = {31'd0, s_dma_dstincr_q};
`NATV_DMA_XFERLEN: s_nmi_rdata_d = s_dma_xferlen_q;
`NATV_DMA_STATUS: s_nmi_rdata_d = {31'd0, s_dma_status_q};
default: s_nmi_rdata_d = s_nmi_rdata_q;
Expand All @@ -164,14 +195,18 @@ module nmi_dma (


dma_core u_dma_core (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.srcaddr_i(s_dma_srcaddr_q),
.dstaddr_i(s_dma_dstaddr_q),
.xferlen_i(s_dma_xferlen_q),
.start_i (s_xfer_start),
.done_o (s_xfer_done),
.nmi (nmi_dma)
.clk_i (clk_i),
.rst_n_i (rst_n_i),
.mode_i (s_dma_mode_q),
.srcaddr_i (s_dma_srcaddr_q),
.srcincr_i (s_dma_srcincr_q),
.dstaddr_i (s_dma_dstaddr_q),
.dstincr_i (s_dma_dstincr_q),
.xferlen_i (s_dma_xferlen_q),
.start_i (s_xfer_start),
.i2s_tx_proc_i(i2s_tx_proc_i),
.done_o (s_xfer_done),
.nmi (nmi_dma)
);

endmodule
30 changes: 26 additions & 4 deletions rtl/ip/native/dma_core.sv
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Expand Up @@ -12,10 +12,14 @@ module dma_core (
// verilog_format: off
input logic clk_i,
input logic rst_n_i,
input logic [1:0] mode_i,
input logic [31:0] srcaddr_i,
input logic srcincr_i,
input logic [31:0] dstaddr_i,
input logic dstincr_i,
input logic [31:0] xferlen_i,
input logic start_i,
input logic i2s_tx_proc_i,
output logic done_o,
nmi_if.master nmi
// verilog_format: on
Expand All @@ -28,6 +32,7 @@ module dma_core (
logic [1:0] s_fsm_d, s_fsm_q;
logic [31:0] s_xfer_cnt_d, s_xfer_cnt_q;
logic [31:0] s_src_addr_d, s_src_addr_q;
logic [31:0] s_dst_addr_d, s_dst_addr_q;
logic [31:0] s_rd_data_d, s_rd_data_q;
logic s_xfer_type_d, s_xfer_type_q; // 0: rd 1: wr

Expand All @@ -36,6 +41,7 @@ module dma_core (
s_fsm_d = s_fsm_q;
s_xfer_cnt_d = s_xfer_cnt_q;
s_src_addr_d = s_src_addr_q;
s_dst_addr_d = s_dst_addr_q;
s_rd_data_d = s_rd_data_q;
s_xfer_type_d = s_xfer_type_q;
// nmi if
Expand All @@ -50,17 +56,24 @@ module dma_core (
if (start_i) begin
s_fsm_d = FSM_XFER;
s_src_addr_d = srcaddr_i;
s_dst_addr_d = dstaddr_i;
end
end
FSM_XFER: begin
nmi.valid = 1'b1;
if (~s_xfer_type_q) begin
nmi.addr = s_src_addr_q;
nmi.valid = 1'b1;
nmi.addr = s_src_addr_q;
if (nmi.ready) begin
s_xfer_type_d = 1'b1;
s_rd_data_d = nmi.rdata;
end
end else begin
unique case (mode_i)
2'd0: nmi.valid = 1'b1;
2'd1: if (i2s_tx_proc_i) nmi.valid = 1'b1;
default: nmi.valid = 1'b1;
endcase

nmi.addr = dstaddr_i;
nmi.wdata = s_rd_data_q;
nmi.wstrb = '1;
Expand All @@ -71,8 +84,9 @@ module dma_core (
s_xfer_cnt_d = '0;
s_fsm_d = FSM_DONE;
end else begin
s_xfer_cnt_d = s_xfer_cnt_q + 3'd4;
s_src_addr_d = s_src_addr_q + 3'd4;
s_xfer_cnt_d = s_xfer_cnt_q + 1'b1;
if (srcincr_i) s_src_addr_d = s_src_addr_q + 3'd4;
if (dstincr_i) s_dst_addr_d = s_dst_addr_q + 3'd4;
end
end
end
Expand All @@ -85,6 +99,7 @@ module dma_core (
s_fsm_d = s_fsm_q;
s_xfer_cnt_d = s_xfer_cnt_q;
s_src_addr_d = s_src_addr_q;
s_dst_addr_d = s_dst_addr_q;
s_rd_data_d = s_rd_data_q;
s_xfer_type_d = s_xfer_type_q;
// nmi if
Expand Down Expand Up @@ -118,6 +133,13 @@ module dma_core (
s_src_addr_q
);

dffr #(32) u_dst_addr_dffr (
clk_i,
rst_n_i,
s_dst_addr_d,
s_dst_addr_q
);

dffr #(32) u_rd_data_dffr (
clk_i,
rst_n_i,
Expand Down
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