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@ptpan ptpan commented Jan 29, 2024

This PR includes changes that will be part of the PyMTL 4.0 release. Here is a list of changes included in this PR (WIP):

  • Support for Verilator 5.016, including Verilog import support and CI setup
  • Revamped Verilog import support to address data corruption / segfaults
  • Support for parallel pytest runs with the xdist module
  • Support for Verilator assertion

ptpan and others added 30 commits November 23, 2023 14:21
ptpan and others added 30 commits February 12, 2024 14:30
The pytest_cmdline_preparse hook is now deprecated. I think there should
be a way to achieve the same effect using pytest_load_initial_conftests

https://docs.pytest.org/en/7.1.x/reference/reference.html#pytest.hookspec.pytest_cmdline_preparse

However, were were using this to hook to prevent *.pyc and __pycache__
files from being generated. I think it is fine for now to just go back
to generating these files.
Improve index handling in Bits and Signal classes
We were using this in our generated Verilog test bench:

  always #(`CYCLE_TIME/2) clk = ~clk;

But if CYCLE_TIME is an odd integer (say 9) this would result in integer
division and round down (i.e., with a cycle time of 9 we would end up with
a clock period of 8!). This doesn't matter unless we are doing back-
annotated gate-level simulation _and_ we use an odd integer clock period
which is why we never detected this bug before. The fix is to simply
force floating point division.

  always #((`CYCLE_TIME*1.0)/2) clk = ~clk;
We were seeing a bug where if you ran a bunch of tests with --dump-vcd
PyMTL3 would only dump the VCD for the first test, although every once
and a while it would indeed dump VCD files for the every test. This
seems to have something to do with the shared library. The cleanest
fix seems to be to avoid hard coding the VCD file name in the generated
PyMTL wrapper and instead to dynamically get the VCD file name from
the metadata.
PyMTL3 was generating an incorrect VCD format that just happened to
work with GTKWave. The old version would output nets as:

b0b0 !
b0b0001 $

So every net had an extra b0 at the beginning. In addition, single-bit
nets should be represented by either 0 or 1 and then the symbol with
no space. This pull request fixes this issue so that PyMTL3 now outputs:

0!
b0001 $
We had to do this kind of craziness to avoid Verilator segfault:

  try:

    t( 0x00, '?'  )
    t( 0x13, 0x01 )
    t( 0x27, 0x14 )
    t( 0x00, 0x28 )
    t( 0x00, 0x01 )
    t( 0x00, 0x01 )

  finally:

    model.finalize()

And we saw segfaults when we tried instantiating the same Verilog
module twice and then using PyMTL for the composition. Peitian
dug into this and provided a fix.

Peitian writes: "This is a change to the C wrapper such that we don't
always create a new VerilatedContext everytime we need to create a new
instance of the model; instead, this change uses a globally shared
VerilatedContext guarded by a reference counter. Based on what I saw I
think we were not managing contexts correctly... This specific segfault
only seems to happen when two instances of the same model are finalized
back to back."
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4 participants