feat: complete VFP support — f32 pseudo-ops and f64 double-precision#47
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feat: complete VFP support — f32 pseudo-ops and f64 double-precision#47
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Implement remaining f32 pseudo-operations (ceil, floor, trunc, nearest, min, max, copysign) and full f64 double-precision VFP encoding for both ARM32 and Thumb-2 modes. f32 pseudo-ops: - F32Ceil/Floor/Trunc/Nearest via VCVT.S32.F32 + VCVT.F32.S32 sequence - F32Min/Max via VMOV + VCMP + VMRS + conditional VMOV - F32Copysign via VMOV to GP regs, AND/BIC/ORR, VMOV back f64 double-precision (D0-D15): - Arithmetic: VADD.F64, VSUB.F64, VMUL.F64, VDIV.F64 - Unary: VABS.F64, VNEG.F64, VSQRT.F64 - Pseudo-ops: ceil, floor, trunc, nearest, min, max, copysign - Comparisons: VCMP.F64 + VMRS + conditional MOV sequence - Load/Store: VLDR.64, VSTR.64 (cp11 encoding) - Constants: MOVW+MOVT (lo32) + MOVW+MOVT (hi32) + VMOV Dd, Rlo, Rhi - Conversions: VCVT.F64.S32/U32, VCVT.F64.F32, VCVT.S32/U32.F64 - Reinterpret: VMOV Dd, Rlo, Rhi / VMOV Rlo, Rhi, Dm Instruction selector: - D-register allocator (D0-D15, wrapping) - has_double_precision() gate for f64 instruction selection - f32 pseudo-ops now generate VFP sequences instead of errors 663 tests pass (31 new), clippy clean, fmt clean. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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PR #47 implemented f32 rounding pseudo-ops but had two bugs: 1. The rounding mode values for ceil (0b01) and floor (0b10) were swapped 2. All rounding modes used VCVTR.S32.F32 which always truncates toward zero, ignoring the mode parameter entirely Fix by properly manipulating the FPSCR rounding mode bits [23:22] for ceil/floor/nearest, using the non-R variant of VCVT.S32.F32 (bit[7]=0) which honours the FPSCR rounding mode, then restoring FPSCR afterward. Trunc continues to use VCVTR (the R variant). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
Completes VFP floating-point support (closes #42). PR #41 added basic f32 arithmetic; this adds the remaining operations.
f32 pseudo-ops (were errors, now real multi-instruction sequences)
f32.ceil/floor/trunc/nearest→ VCVT round-trip sequencesf32.min/max→ VCMP + VMRS + conditional VMOVf32.copysign→ VMOV to GP registers, bit manipulation, VMOV backf64 double-precision (new)
has_double_precision_fpu()(M7DP only)Changes
arm_encoder.rsinstruction_selector.rsf32_operations_test.rsf32_vfp_encoding_test.rsTest plan
cargo clippycleancargo fmt --checkclean🤖 Generated with Claude Code