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…ions Add compile-time validation that ensures the compiler never emits ARM instructions unsupported by the target platform. This is critical for correctness: e.g., Cortex-M3/M4 (no FPU) must not receive VFP instructions, and single-precision targets must not receive F64 ops. Changes: - Add ISA capability methods to CortexMVariant (has_dsp, has_fpu, has_trustzone, has_helium) and TargetSpec (has_single/double_precision) - Add ArmOp::requires_fpu() and requires_double_precision_fpu() methods with human-readable instruction_name() for error messages - Add validate_instructions() pass between instruction selection and encoding in the compilation pipeline - Add UnsupportedInstruction error variant to synth-core - Add 18 new tests covering ISA feature queries, instruction validation, and end-to-end compilation gating across M3/M4/M4F/M7DP targets Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Recreating with correct branch mapping |
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Summary
rivet.yamlproject configuration with common, stpa, aspice, dev schemas53 total artifacts,
rivet validatepasses with 24 warnings (expected for initial setup — missing STPA steps 2-4, NFRs lacking verification backlinks).Artifact Summary
Test plan
rivet validatepasses (PASS, 24 warnings)rivet statsshows 53 artifacts🤖 Generated with Claude Code