v2.3.0

What's Changed

• Revert "Introduce job queues for source/sink modules (supersedes #48)" by @FrancescoConti in #68
• Struct-to-interface converters for MAGIA by @FrancescoConti in #73

Full Changelog: v2.2.0...v2.3.0

v2.2.0

What's Changed

• Update Bender.yml to hwpe-stream 1.9.0 by @FrancescoConti in #52
• Added parameter pass-trough to HCI Core Source and Sink. by @Lynx005F in #46
• Add source / sink modules for replication for error detection. by @Lynx005F in #40
• Remove HCI core FIFO outdated parameters. by @yvantor in #55
• Multiple HWPE support + ECC by @FrancescoConti in #53
• Minor Fixes for ECC-HCI (Follow-up on #53) by @LuigiGhionda in #57
• Fixed HCI Core Static MUX by @Jayanth2209 in #62
• Addr Misaligned Fifo generation by @irene-ik in #64
• Prevent spurious writes when byte enable is all zero. by @yvantor in #58
• Introduce job queues for source/sink modules (supersedes #48) by @FrancescoConti in #65
• Revert "Fixed HCI Core Static MUX" by @FrancescoConti in #67

New Contributors

• @Lynx005F made their first contribution in #46
• @LuigiGhionda made their first contribution in #57
• @Jayanth2209 made their first contribution in #62
• @irene-ik made their first contribution in #64

Full Changelog: v2.1.2...v2.2.0

v2.1.2

What's Changed

• [update] optimize bandwidth for multiplexed aligned and misaligned sources by @arpansur in #44
• Disable assertions for VCS by @gamzeisl in #47
• Update STYLE.md by @FrancescoConti in #49
• Fix range underflows in logic vectors by @Scheremo in #50

New Contributors

• @arpansur made their first contribution in #44
• @gamzeisl made their first contribution in #47
• @Scheremo made their first contribution in #50

Full Changelog: v2.1.1...v2.1.2

astral-v1.0

What's Changed

• [update] optimize bandwidth for multiplexed aligned and misaligned sources by @arpansur in #44
• Disable assertions for VCS by @gamzeisl in #47

New Contributors

• @arpansur made their first contribution in #44
• @gamzeisl made their first contribution in #47

Full Changelog: v2.1.1...astral-v1.0

v2.1.1

What's Changed

• Relax assertion on IW in OoO mux and connect ECC signals in the interconnect. by @yvantor in #38

Full Changelog: v2.1.0...v2.1.1

v2.1.0

What's Changed

• Remove automatic parameter prop by @FrancescoConti in #32
• Fix #34 by keeping winner_d stable in OOO Mux if there is an input request by @FrancescoConti in #37

Full Changelog: v2.0.3...v2.1.0

v2.0.3

What's Changed

• Dynamic Mux: Fix r_* signals to be synchronous with r_data, not gnt by @FrancescoConti in #28
• Export rtl/common include dir to dependent packages by @FrancescoConti in #30

Full Changelog: v2.0.2...v2.0.3

v2.0.2

Fix an issue with Vivado synthesis not using the correct helper macros to derive parameters from interfaces.

v2.0.0

Rationalized HCI protocol and interface IPs.

• rationalize the naming scheme for HCI:
  1. hci_hwpe_interconnect -> hci_router
  2. hci_hwpe_reorder -> hci_router_reorder
  3. hci_shallow_interconnect -> hci_arbiter
• remove boffs signal
• add proper ID signal id and r_id
• add ECC signal ecc and r_ecc
• sanitize {slave,master} names to {target,initiator}
• rename lrdy to r_ready
• deprecate hci_mem_intf and replace it with hci_core_intf
• replace usage of hwpe_stream_intf_tcdm with hci_core_intf
• invert direction of interface dimensions for better adherence to synthesis guidelines
• rationalize parametrization, using interfaces to pass parameters
• cleanup

v1.0.9

Last release of HCIv1 without breaking changes (v1.1) and without redesign (v2.0)