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Solve struct-assignment-related elaboration errors #9

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6 changes: 2 additions & 4 deletions src/axi_llc_hit_miss.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -372,10 +372,8 @@ module axi_llc_hit_miss #(
);

// inputs to the lock box
assign lock = '{
index: desc_o.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength)+:Cfg.IndexLength],
way_ind: desc_o.way_ind
};
assign lock.index = desc_o.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength)+:Cfg.IndexLength];
assign lock.way_ind = desc_o.way_ind;
// Lock it if a transfer happens on ether channel and no flush!
assign lock_req = ~desc_o.flush & ((miss_valid_o & miss_ready_i) | (hit_valid_o & hit_ready_i));

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20 changes: 9 additions & 11 deletions src/axi_llc_read_unit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -97,19 +97,17 @@ module axi_llc_read_unit #(
logic meta_fifo_pop;

// way_inp assignments
assign way_inp_o = '{
cache_unit: axi_llc_pkg::RChanUnit,
way_ind: desc_q.way_ind,
line_addr: desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength)+:Cfg.IndexLength],
blk_offset: desc_q.a_x_addr[ Cfg.ByteOffsetLength +: Cfg.BlockOffsetLength],
default: '0
}; // other fields not needed, `we` is `1'b0.
assign way_inp_o.cache_unit = axi_llc_pkg::RChanUnit;
assign way_inp_o.way_ind = desc_q.way_ind;
assign way_inp_o.line_addr = desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength)+:Cfg.IndexLength];
assign way_inp_o.blk_offset = desc_q.a_x_addr[ Cfg.ByteOffsetLength +: Cfg.BlockOffsetLength];
assign way_inp_o.data = '0;
assign way_inp_o.strb = '0;
assign way_inp_o.we = '0;

// unlock assignment
assign r_unlock_o = '{
index: desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength)+:Cfg.IndexLength],
way_ind: desc_q.way_ind
};
assign r_unlock_o.index = desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength)+:Cfg.IndexLength];
assign r_unlock_o.way_ind = desc_q.way_ind;

// control
always_comb begin
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22 changes: 9 additions & 13 deletions src/axi_llc_write_unit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -106,21 +106,17 @@ module axi_llc_write_unit #(
);

// way_inp assignments
assign way_inp_o = '{
cache_unit: axi_llc_pkg::WChanUnit,
way_ind: desc_q.way_ind,
line_addr: desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength) +: Cfg.IndexLength],
blk_offset: desc_q.a_x_addr[ Cfg.ByteOffsetLength +: Cfg.BlockOffsetLength],
we: 1'b1,
data: w_chan.data,
strb: w_chan.strb
};
assign way_inp_o.cache_unit = axi_llc_pkg::WChanUnit;
assign way_inp_o.way_ind = desc_q.way_ind;
assign way_inp_o.line_addr = desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength) +: Cfg.IndexLength];
assign way_inp_o.blk_offset = desc_q.a_x_addr[ Cfg.ByteOffsetLength +: Cfg.BlockOffsetLength];
assign way_inp_o.we = 1'b1;
assign way_inp_o.data = w_chan.data;
assign way_inp_o.strb = w_chan.strb;

// assignment of the write unlock fields, which are not set with the control below
assign w_unlock_o = '{
index: desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength) +: Cfg.IndexLength],
way_ind: desc_q.way_ind
};
assign w_unlock_o.index = desc_q.a_x_addr[(Cfg.ByteOffsetLength + Cfg.BlockOffsetLength) +: Cfg.IndexLength];
assign w_unlock_o.way_ind = desc_q.way_ind;

// unit control
always_comb begin
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