Avoid undefined conditions in always_comb.

Bender.lock

@@ -1,16 +1,23 @@
 packages:
+  apb:
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
+    source:
+      Git: https://github.com/pulp-platform/apb.git
+    dependencies:
+    - common_cells
   axi:
-    revision: af8b0ce2653997301b1b792c4c6d207b95f63a56
-    version: 0.39.0-beta.2
+    revision: 4fb5a02ef5c96396ac2157bcaf09bb6a05b6a87d
+    version: null
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
     - tech_cells_generic
   common_cells:
-    revision: b59eca3c1747b28022573e37aa91a151808d1db5
-    version: 1.26.0
+    revision: 53b0b58af2db5bd3c850a7038fae170ed78326bb
+    version: 1.31.1
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -23,16 +30,17 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   register_interface:
-    revision: 9fc63015615acb11111e4bc3e858381e3e72405d
-    version: 0.3.6
+    revision: 146501d80052b61475cdc333d3aab4cd769fd5dc
+    version: 0.3.9
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
+    - apb
     - axi
     - common_cells
   tech_cells_generic:
-    revision: e6226a6f374eb88fed84d4989bb3f066cb470f33
-    version: 0.2.9
+    revision: 298b7297d220ba2601d0f24f684f97ff32f61123
+    version: 0.2.12
     source:
       Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:

Bender.yml

@@ -9,7 +9,7 @@ package:
     - "Wolfgang Roenninger <wroennin@ethz.ch>"
 
 dependencies:
-  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0-beta.2 }
+  axi: { git: "https://github.com/pulp-platform/axi.git", rev: 4fb5a02 }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 }
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
   register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.6 }
@@ -24,6 +24,12 @@ sources:
   # levels 1 and 0, etc. Files within a level are ordered alphabetically.
   # Level 0
   - src/axi_llc_pkg.sv
+  - src/axi_llc_sram_data.sv
+  - src/axi_llc_sram_tag.sv
+  # - src/axi_llc_sram_data_fpga.sv
+  # - src/axi_llc_sram_tag_fpga.sv
+  - src/axi_llc_index_assigner.sv
+  - src/axi_llc_trdl_index.sv
   - src/axi_llc_burst_cutter.sv
   - src/axi_llc_data_way.sv
   - src/axi_llc_merge_unit.sv
@@ -45,12 +51,14 @@ sources:
   - src/axi_llc_ways.sv
   - src/hit_miss_detect/axi_llc_tag_store.sv
   # Level 2
-  - src/axi_llc_config.sv
+  - src/axi_llc_config_pat.sv
+  - src/axi_llc_config_no_pat.sv
   - src/axi_llc_hit_miss.sv
   # Level 3
   - src/axi_llc_top.sv
   # Level 4
   - src/axi_llc_reg_wrap.sv
+  - test/synth_axi_llc.sv
 
 
   - target: test
@@ -59,4 +67,5 @@ sources:
     files:
       # Level 0:
       - test/tb_axi_llc.sv
+      - test/synth_axi_llc.sv
 

Makefile

@@ -10,6 +10,16 @@ PYTHON ?= python3
 REGGEN_PATH  = $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 REGGEN	     = $(PYTHON) $(REGGEN_PATH)
 
+REGWIDTH            = 64
+CACHENUMLINES       = 256
+MAXPARTITION        = 16
+CACHE_PARTITION		= 1
+AXI_LLC_REGS_PATH   = data/axi_llc_regs.py
+TYPEDEF_PATH        = include/axi_llc/typedef.py
+ASSIGN_PATH         = include/axi_llc/assign.py
+AXI_LLC_CONFIG_PATH = src/axi_llc_config_pat.py
+TB_CONFIG_REG_ADDR_PATH = test/tb_config_reg_addr.py
+
 .PHONY: all clean
 
 all: help
@@ -44,10 +54,23 @@ help:
 # Registers
 # --------------
 
-regs:
+regs:set_partition_config
 	$(REGGEN) -r --outdir src/ data/axi_llc_regs.hjson
 	$(REGGEN) --cdefines --outfile sw/include/axi_llc_regs.h data/axi_llc_regs.hjson
 
+
+# -------------------------
+# Set-Based Cache Partition
+# -------------------------
+
+set_partition_config:
+	$(PYTHON) $(AXI_LLC_REGS_PATH) $(REGWIDTH) $(CACHENUMLINES) $(MAXPARTITION) ${CACHE_PARTITION}
+	$(PYTHON) $(TYPEDEF_PATH) $(REGWIDTH) $(CACHENUMLINES) $(MAXPARTITION) ${CACHE_PARTITION}
+	$(PYTHON) $(ASSIGN_PATH) $(REGWIDTH) $(CACHENUMLINES) $(MAXPARTITION) ${CACHE_PARTITION}
+# 	$(PYTHON) $(AXI_LLC_CONFIG_PATH) $(REGWIDTH) $(CACHENUMLINES) $(MAXPARTITION)
+	$(PYTHON) $(TB_CONFIG_REG_ADDR_PATH) $(REGWIDTH) $(CACHENUMLINES) $(MAXPARTITION)
+
+
 # --------------
 # QuestaSim
 # --------------

data/axi_llc_regs.hjson

@@ -161,6 +161,75 @@
       fields: [
         {bits: "0:0", name: "done", desc: "BIST successfully completed"}
       ]
-    }
+    },
+    { name: "CFG_FLUSH_PARTITION_LOW",
+      desc: "Index-based Partition Flush Configuration [31:0] (lower 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", resval: 4294967295, name: "low", desc: "lower 32 bit"}
+      ]
+    },
+    { name: "CFG_FLUSH_PARTITION_HIGH",
+      desc: "Index-based Partition Flush Configuration [63:32] (upper 32 bit)",
+      swaccess: "rw",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", resval: 4294967295, name: "high", desc: "upper 32 bit"}
+      ]
+    },
+    { multireg: {
+         name: "CFG_SET_PARTITION_LOW",
+         desc: "Index-based Partition Configuration [31:0] (lower 32 bit)",
+         count: "2",
+         cname: "AXI_LLC"
+         swaccess: "rw",
+         hwaccess: "hrw",
+         fields: [
+         {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    }},
+    { multireg: {
+         name: "CFG_SET_PARTITION_HIGH",
+         desc: "Index-based Partition Configuration [63:32] (higher 32 bit)",
+         count: "2",
+         cname: "AXI_LLC"
+         swaccess: "rw",
+         hwaccess: "hrw",
+         fields: [
+         {bits: "31:0", name: "high", desc: "higher 32 bit"}
+      ]
+    }},
+    { name: "COMMIT_PARTITION_CFG",
+      desc: "Commit the set partition configuration",
+      swaccess: "rw1s",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "0", name: "commit", desc: "commit set partition configuration"}
+      ]
+    },
+    {skipto: "0x6c"},
+    { multireg: {
+      name: "FLUSHED_SET_LOW",
+      desc: "Index-based Flushed Flag (lower 32 bit)",
+      count: "4",
+      cname: "AXI_LLC"
+      swaccess: "ro",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "low", desc: "lower 32 bit"}
+      ]
+    }},
+    { multireg: {
+      name: "FLUSHED_SET_HIGH",
+      desc: "Index-based Flushed Flag (upper 32 bit)",
+      count: "4",
+      cname: "AXI_LLC"
+      swaccess: "ro",
+      hwaccess: "hrw",
+      fields: [
+        {bits: "31:0", name: "high", desc: "upper 32 bit"}
+      ]
+    }}
   ]
 }