Add DC contingencies #3639
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Add DC contingencies #3639
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Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
added 3 commits
November 5, 2025 09:40
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
Signed-off-by: Denis Bonnand <[email protected]>
rolnico
requested changes
Nov 17, 2025
iidm/iidm-api/src/main/java/com/powsybl/iidm/network/DcTerminal.java
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iidm/iidm-api/src/main/java/com/powsybl/iidm/network/DcTerminal.java
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iidm/iidm-api/src/main/java/com/powsybl/iidm/network/DcTerminal.java
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iidm/iidm-api/src/main/java/com/powsybl/iidm/network/DcTerminal.java
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iidm/iidm-impl/src/main/java/com/powsybl/iidm/network/impl/DcTerminalImpl.java
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iidm/iidm-impl/src/main/java/com/powsybl/iidm/network/impl/DcTopologyModel.java
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iidm/iidm-impl/src/test/java/com/powsybl/iidm/network/impl/DcTopologyTraverseTest.java
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iidm/iidm-modification/src/main/java/com/powsybl/iidm/modification/tripping/DcLineTripping.java
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...fication/src/main/java/com/powsybl/iidm/modification/tripping/TrippingTopologyTraverser.java
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iidm/iidm-tck/src/test/java/com/powsybl/iidm/network/tck/AbstractDcLineTest.java
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Signed-off-by: Denis Bonnand <[email protected]>
geofjamg
previously approved these changes
Nov 19, 2025
olperr1
requested changes
Nov 24, 2025
iidm/iidm-impl/src/main/java/com/powsybl/iidm/network/impl/DcTerminalImpl.java
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rolnico
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Nov 24, 2025
iidm/iidm-impl/src/test/java/com/powsybl/iidm/network/impl/DcTopologyTraverseTest.java
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Signed-off-by: Denis Bonnand <[email protected]>
added 2 commits
November 24, 2025 16:26
Signed-off-by: Denis Bonnand <[email protected]>
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Please check if the PR fulfills these requirements
Does this PR already have an issue describing the problem?
No
What kind of change does this PR introduce?
Feature
What is the current behavior?
Powsybl core cannot modelize contingencies on DC detailed components
What is the new behavior (if this is a feature change)?
It is now possible to create contingencies on DcLine, VoltageSourceConverter, DcGround and DcNode
Does this PR introduce a breaking change or deprecate an API?
Other information: