Documentation

Documentation has moved to https://github.com/phanrahan/magma/tree/master/doc

THE REST OF THIS PAGE IS OUT OF DATE

Installation

Getting Started

• Full Adder
• TFF
• Counter
• Verilog

Types, Operators, and Functions

• Type hierarchy

  • Clock
  • Bit
  • Array(n,T)
    • Bits(n) = Array(n, Bit)
      • SInt(n)
      • UInt(n)
  • Tuple(name0, T0, name1, T1, …, namen, Tn)

• Operators

  • All
    • == !=
  • Bit
    • & | ^ ~
  • Bits
    • & | ^ ~ >> <<
  • UInt, Sint
    • >>
    • +, -, *, /
    • < <= > >=

• Functions

  • concat
  • repeat
  • zext
  • sext

• Mantle

Circuits

• Circuits
• Circuit instances
• Wiring
• Naming conventions

Circuit Metaprogramming

• Declarations: DeclareCircuit
• Definitions: DefineCircuit, EndCircuit
• class SubCircuit(Circuit)
• Verilog declatations: DeclareFromVerilog, DeclareFromVerilogFile
• Verilog definitions: DefineFromVerilog, DefineFromVerilogFile, DefineFromTemplatedVerilog, DefineFromTemplatedVerilogFile

Higher-Order Circuit functions

• compose
• curry, uncurry
• fork, join, flat
• fold, scan
• braid
• row, col, map_

Appendix: Running the Python Simulator

Appendix: Running on the icestick

Appendix: Logisym