Ndh/vivado reuse

.buckconfig

@@ -17,4 +17,13 @@ target_platform_detector_spec = target:root//...->prelude//platforms:default
 ignore = .git
 
 [build]
-execution_platforms = prelude//platforms:default
+execution_platforms = prelude//platforms:default
+
+[buck2_re_client]
+engine_address       = grpc://172.21.252.165:50051
+action_cache_address = grpc://172.21.252.165:50051
+cas_address          = grpc://172.21.252.165:50051
+tls = false
+instance_name = main
+enabled = false
+capabilities = true

.buckconfig_cache

@@ -0,0 +1,29 @@
+[repositories]
+root = .
+prelude = prelude
+toolchains = toolchains
+none = none
+
+[repository_aliases]
+config = prelude
+fbcode = none
+fbsource = none
+buck = none
+
+[parser]
+target_platform_detector_spec = target:root//...->prelude//platforms:default
+
+[project]
+ignore = .git
+
+[build]
+execution_platforms = prelude//platforms:default
+
+[buck2_re_client]
+engine_address       = grpc://172.21.252.165:50051
+action_cache_address = grpc://172.21.252.165:50051
+cas_address          = grpc://172.21.252.165:50051
+tls = false
+instance_name = main
+enabled = true
+capabilities = true

hdl/projects/cosmo_seq/BUCK

@@ -1,6 +1,6 @@
 load("//tools:hdl.bzl", "vhdl_unit", "black_box")
 load("//tools:rdl.bzl", "rdl_file")
-load("//tools:vivado.bzl", "vivado_bitstream")
+load("//tools:vivado.bzl", "vivado_bitstream", "vivado_ip")
 
 rdl_file(
     name = "cosmo_seq_top_rdl",
@@ -44,6 +44,13 @@ vhdl_unit(
     standard = "2019",
 )
 
+vivado_ip(
+    name = "cosmo_pll_ip",
+    tcl = "xilinx_ip_gen/cosmo_pll_ip_gen.tcl",
+    module_name = "cosmo_pll",
+    part = "xc7s100fgga484-1",
+)
+
 
 vhdl_unit(
     name = "cosmo_seq_top",
@@ -71,7 +78,8 @@ vivado_bitstream(
     top_entity_name="cosmo_seq_top",
     top= ":cosmo_seq_top",
     part= "xc7s100fgga484-1",
+    ip=[":cosmo_pll_ip"],
     constraints=glob(["*.xdc"]),
-    pre_synth_tcl_files=glob(["xilinx_ip_gen/*.tcl"]),
+    #pre_synth_tcl_files=glob(["xilinx_ip_gen/*.tcl"]),
     #post_synth_tcl_files=glob(["*ila.tcl"]),
 )

hdl/projects/cosmo_seq/xilinx_ip_gen/cosmo_pll_ip_gen.tcl

@@ -0,0 +1,31 @@
+# Generate the PLL (copied from tcl console using the IP generator)
+# with name and dir adjusted
+
+# Get tclargs here
+set name [lindex $argv 0]
+set dir [lindex $argv 1]
+
+# generate IP
+create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $name -dir $dir
+set_property -dict [list \
+  CONFIG.CLKIN1_JITTER_PS {200.0} \
+  CONFIG.CLKOUT1_JITTER {154.207} \
+  CONFIG.CLKOUT1_PHASE_ERROR {164.985} \
+  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000} \
+  CONFIG.CLKOUT2_JITTER {142.107} \
+  CONFIG.CLKOUT2_PHASE_ERROR {164.985} \
+  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
+  CONFIG.CLKOUT2_USED {true} \
+  CONFIG.CLK_OUT1_PORT {clk_125m} \
+  CONFIG.CLK_OUT2_PORT {clk_200m} \
+  CONFIG.Component_Name {$name} \
+  CONFIG.MMCM_CLKFBOUT_MULT_F {20.000} \
+  CONFIG.MMCM_CLKIN1_PERIOD {20.000} \
+  CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
+  CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} \
+  CONFIG.MMCM_CLKOUT1_DIVIDE {5} \
+  CONFIG.NUM_OUT_CLKS {2} \
+  CONFIG.PRIMARY_PORT {clk_50m} \
+  CONFIG.PRIM_IN_FREQ {50} \
+] [get_ips $name]
+synth_ip [get_ips $name]

tools/hdl.bzl

@@ -90,12 +90,12 @@ def _hdl_unit_impl(ctx: AnalysisContext) -> list[Provider]:
         cmd.add(vunit_gen)
         cmd.add("--input", ctx.attrs.srcs[0])
         cmd.add("--output", out_codec_pkg.as_output())
-        ctx.actions.run(cmd, category="vunit_codec_gen")
+        ctx.actions.run(cmd, category="vunit_codec_gen",  local_only = True, allow_cache_upload=True)
         providers.append(GenVHDLInfo(src=out_codec_pkg))
 
     # do VUnit stuff here if this is a test bench
-    # Note that this is not acutally generated in the buck_out/ folder
-    # After playing with this a bit, putting the vunitout folder in the
+    # Note that this is not actually generated in the buck_out/ folder
+    # After playing with this a bit, putting the vunit-out folder in the
     # buck_out/ folder can be done (see info below) but is annoying since
     # we get a new buck_out/ each time the input changes meaning we have
     # to re-compile everything. We *could* attempt to do more here in buck
@@ -125,7 +125,7 @@ def _hdl_unit_impl(ctx: AnalysisContext) -> list[Provider]:
         cmd.add("--output", out_run_py.as_output())
         if ctx.attrs.simulator:
             cmd.add("--simulator", ctx.attrs.simulator)
-        ctx.actions.run(cmd, category="vunit")
+        ctx.actions.run(cmd, category="vunit",  local_only = True, allow_cache_upload=True)
 
         # Left here as an example of how to put the vunit_out
         # folder into buck_out. This turns out to be a bit annoying

tools/rdl.bzl

@@ -84,6 +84,8 @@ def _rdl_file_impl(ctx):
         ctx.actions.run(
             rdl_out_gen,
             category="rdl",
+            local_only = True,
+            allow_cache_upload=True,
         )
 
         # Build TSets for the generated VHDL files as a list of VHDLFileInfo

tools/replatform/defs.bzl

@@ -0,0 +1,64 @@
+# Copyright (c) Meta Platforms, Inc. and affiliates.
+#
+# This source code is licensed under both the MIT license found in the
+# LICENSE-MIT file in the root directory of this source tree and the Apache
+# License, Version 2.0 found in the LICENSE-APACHE file in the root directory
+# of this source tree.
+
+def _execution_platform_impl(ctx: AnalysisContext) -> list[Provider]:
+    constraints = dict()
+    constraints.update(ctx.attrs.cpu_configuration[ConfigurationInfo].constraints)
+    constraints.update(ctx.attrs.os_configuration[ConfigurationInfo].constraints)
+    cfg = ConfigurationInfo(constraints = constraints, values = {})
+
+    name = ctx.label.raw_target()
+    platform = ExecutionPlatformInfo(
+        label = name,
+        configuration = cfg,
+        executor_config = CommandExecutorConfig(
+            local_enabled = True,
+            remote_enabled = False,
+            use_windows_path_separators = ctx.attrs.use_windows_path_separators,
+        ),
+    )
+
+    return [
+        DefaultInfo(),
+        platform,
+        PlatformInfo(label = str(name), configuration = cfg),
+        ExecutionPlatformRegistrationInfo(platforms = [platform]),
+    ]
+
+execution_platform = rule(
+    impl = _execution_platform_impl,
+    attrs = {
+        "cpu_configuration": attrs.dep(providers = [ConfigurationInfo]),
+        "os_configuration": attrs.dep(providers = [ConfigurationInfo]),
+        "use_windows_path_separators": attrs.bool(),
+    },
+)
+
+def _host_cpu_configuration() -> str:
+    arch = host_info().arch
+    if arch.is_aarch64:
+        return "prelude//cpu:arm64"
+    elif arch.is_arm:
+        return "prelude//cpu:arm32"
+    elif arch.is_i386:
+        return "prelude//cpu:x86_32"
+    else:
+        return "prelude//cpu:x86_64"
+
+def _host_os_configuration() -> str:
+    os = host_info().os
+    if os.is_macos:
+        return "prelude//os:macos"
+    elif os.is_windows:
+        return "prelude//os:windows"
+    else:
+        return "prelude//os:linux"
+
+host_configuration = struct(
+    cpu = _host_cpu_configuration(),
+    os = _host_os_configuration(),
+)