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    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      Apache License 2.0
      593592810Updated Mar 30, 2026Mar 30, 2026
    • AraXL

      Public
      A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
      C
      Other
      4612Updated Mar 30, 2026Mar 30, 2026
    • iis-typst

      Public
      IIS templates in Typst
      Typst
      Apache License 2.0
      0000Updated Mar 30, 2026Mar 30, 2026
    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      Apache License 2.0
      4114037Updated Mar 30, 2026Mar 30, 2026
    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      Apache License 2.0
      61843Updated Mar 30, 2026Mar 30, 2026
    • magia-sdk

      Public
      C
      9406Updated Mar 30, 2026Mar 30, 2026
    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      Verilog
      Other
      1053241825Updated Mar 30, 2026Mar 30, 2026
    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      C
      Other
      176503867Updated Mar 30, 2026Mar 30, 2026
    • wakelet

      Public
      Standalone, tiny, and low-power infrastructure to boost the HWPE flexiblity for always-on domains.
      Tcl
      Apache License 2.0
      2200Updated Mar 30, 2026Mar 30, 2026
    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is a…
      Tcl
      Other
      32124165Updated Mar 30, 2026Mar 30, 2026
    • picobello

      Public
      whatever it means
      C
      Other
      121550Updated Mar 30, 2026Mar 30, 2026
    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      Other
      9222217Updated Mar 30, 2026Mar 30, 2026
    • SystemVerilog
      Other
      2500Updated Mar 28, 2026Mar 28, 2026
    • The multi-core cluster of a PULP system.
      SystemVerilog
      Other
      3511353Updated Mar 28, 2026Mar 28, 2026
    • Python
      Apache License 2.0
      41012Updated Mar 27, 2026Mar 27, 2026
    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      C
      Apache License 2.0
      6131536Updated Mar 27, 2026Mar 27, 2026
    • C
      3202Updated Mar 27, 2026Mar 27, 2026
    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      Other
      3521.5k5322Updated Mar 27, 2026Mar 27, 2026
    • ace

      Public
      SystemVerilog
      Other
      72100Updated Mar 27, 2026Mar 27, 2026
    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      Apache License 2.0
      55274234Updated Mar 26, 2026Mar 26, 2026
    • datamover

      Public
      SystemVerilog
      Other
      2101Updated Mar 26, 2026Mar 26, 2026
    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      Python
      41641618Updated Mar 26, 2026Mar 26, 2026
    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      SystemVerilog
      Other
      10121827Updated Mar 25, 2026Mar 25, 2026
    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      Other
      201456Updated Mar 24, 2026Mar 24, 2026
    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      93303Updated Mar 24, 2026Mar 24, 2026
    • A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      Other
      133701Updated Mar 24, 2026Mar 24, 2026
    • chimera

      Public
      Python
      Apache License 2.0
      92395Updated Mar 23, 2026Mar 23, 2026
    • Common SystemVerilog components
      SystemVerilog
      Other
      1947293513Updated Mar 23, 2026Mar 23, 2026
    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      Apache License 2.0
      63501Updated Mar 20, 2026Mar 20, 2026
    • C++
      17k1471Updated Mar 17, 2026Mar 17, 2026
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