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    321 repositories

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •59•359•28•10•Updated Mar 30, 2026Mar 30, 2026

    • AraXL

      Public
      A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
      C
      •
      Other
      •4•6•1•2•Updated Mar 30, 2026Mar 30, 2026

    • iis-typst

      Public
      IIS templates in Typst
      typsttypst-template
      typsttypst-template
      Typst
      •
      Apache License 2.0
      •0•0•0•0•Updated Mar 30, 2026Mar 30, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •41•140•3•7•Updated Mar 30, 2026Mar 30, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •6•18•4•3•Updated Mar 30, 2026Mar 30, 2026

    • magia-sdk

      Public
      C
      •9•4•0•6•Updated Mar 30, 2026Mar 30, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •105•324•18•25•Updated Mar 30, 2026Mar 30, 2026

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvector
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •176•503•86•7•Updated Mar 30, 2026Mar 30, 2026

    • wakelet

      Public
      Standalone, tiny, and low-power infrastructure to boost the HWPE flexiblity for always-on domains.
      Tcl
      •
      Apache License 2.0
      •2•2•0•0•Updated Mar 30, 2026Mar 30, 2026

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is a…
      casicfpga
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •32•124•16•5•Updated Mar 30, 2026Mar 30, 2026

    • picobello

      Public
      whatever it means
      aiacceleratorsystemverilog
      aiacceleratorsystemverilogrisc-vnoc
      C
      •
      Other
      •12•15•5•0•Updated Mar 30, 2026Mar 30, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •922•22•1•7•Updated Mar 30, 2026Mar 30, 2026

    • Insitu-Cache

      Public
      SystemVerilog
      •
      Other
      •2•5•0•0•Updated Mar 28, 2026Mar 28, 2026

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •35•113•5•3•Updated Mar 28, 2026Mar 28, 2026

    • pulp-actions

      Public
      Python
      •
      Apache License 2.0
      •4•10•1•2•Updated Mar 27, 2026Mar 27, 2026

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •61•315•3•6•Updated Mar 27, 2026Mar 27, 2026

    • ManyRVData

      Public
      C
      •3•2•0•2•Updated Mar 27, 2026Mar 27, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •352•1.5k•53•22•Updated Mar 27, 2026Mar 27, 2026

    • ace

      Public
      SystemVerilog
      •
      Other
      •7•21•0•0•Updated Mar 27, 2026Mar 27, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •55•274•23•4•Updated Mar 26, 2026Mar 26, 2026

    • datamover

      Public
      SystemVerilog
      •
      Other
      •2•1•0•1•Updated Mar 26, 2026Mar 26, 2026

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      mcutinymlml-compiler
      Python
      •41•64•16•18•Updated Mar 26, 2026Mar 26, 2026

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilog
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •101•218•2•7•Updated Mar 25, 2026Mar 25, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •20•14•5•6•Updated Mar 24, 2026Mar 24, 2026

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •93•3•0•3•Updated Mar 24, 2026Mar 24, 2026

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •13•37•0•1•Updated Mar 24, 2026Mar 24, 2026

    • chimera

      Public
      Python
      •
      Apache License 2.0
      •9•23•9•5•Updated Mar 23, 2026Mar 23, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •194•729•35•13•Updated Mar 23, 2026Mar 23, 2026

    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      •
      Apache License 2.0
      •6•35•0•1•Updated Mar 20, 2026Mar 20, 2026

    • llvm-project

      Public
      C++
      •17k•14•7•1•Updated Mar 17, 2026Mar 17, 2026
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