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@Cal-Poly-RAMP Cal Poly Computer Architecture Research Project (CARP)

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    16 repositories

    • cal-poly-ramp.github.io

      Public
      Website for the RAMP framework
      Python
      •0•0•0•0•Updated Jan 29, 2026Jan 29, 2026

    • carp-core

      Public
      The CARP Core is a 32-bit RV32IMAC_Zicsr_Zifencei_Zicntr microprocessor implementation
      SystemVerilog
      •16•2•0•0•Updated Jan 24, 2026Jan 24, 2026

    • carp-tools

      Public
      A docker image hosting the RISC-V GNU toolchain, as well as Spike, PK, and the usual host of open-source ASIC tools. (see IIC-OSIC-TOOLS Docker Container for a …
      Verilog
      •0•0•0•0•Updated Dec 24, 2025Dec 24, 2025

    • carp_tools

      Public
      This is a containerized environment containing OSS CAD Suite and the RISC-V Toolchain, used for developing CARP IP.
      Shell
      •2•0•0•0•Updated Sep 29, 2025Sep 29, 2025

    • carp_pcb

      Public
      C
      •55•0•0•0•Updated Jun 13, 2025Jun 13, 2025

    • .github

      Public
      0•0•0•0•Updated May 17, 2024May 17, 2024

    • sky130_sram_macros

      Public
      SourcePawn
      •
      Apache License 2.0
      •16•0•0•0•Updated Feb 18, 2024Feb 18, 2024

    • cocotbext-wishbone

      Public
      Python
      •
      Apache License 2.0
      •14•0•0•0•Updated Feb 17, 2024Feb 17, 2024

    • basejump_stl

      Public
      BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      •
      Other
      •113•0•0•0•Updated Feb 17, 2024Feb 17, 2024

    • tapeout-ci-2311

      Public template
      caravel-user repository for November 6, 2023 tapeout
      Verilog
      •
      Apache License 2.0
      •1•1•3•0•Updated Feb 1, 2024Feb 1, 2024

    • CARPOpenLane

      Public
      OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design explor…
      Verilog
      •
      Apache License 2.0
      •416•1•0•0•Updated Jun 14, 2023Jun 14, 2023

    • sram22-hammer

      Public
      A configurable SRAM generator
      Rust
      •
      BSD 3-Clause "New" or "Revised" License
      •7•0•0•0•Updated May 16, 2023May 16, 2023

    • qspiflash

      Public
      A set of Wishbone Controlled SPI Flash Controllers
      Verilog
      •26•0•0•0•Updated May 12, 2023May 12, 2023

    • riscv32-csr

      Public
      C++
      •0•0•0•0•Updated Jan 17, 2023Jan 17, 2023

    • ramp-core

      Public
      RAMP's out of order RV32G processor, implemented with PyMTL3
      Python
      •3•2•0•0•Updated Dec 28, 2022Dec 28, 2022

    • style-guide

      Public
      The SystemVerilog style guide for the RAMP framework.
      0•0•0•0•Updated Oct 13, 2022Oct 13, 2022