The five stage processor implementation included the pipeline registers IF/ID, ID/EX, EX/MEM, and MEM/WB. By 'basic' components I mean register file, instruction memory, data memory, ALU, two adders, shift left components, and a 16 to 32 bit sign extend unit. For the project, we were provided test data for our registers that we used to compare whether or not our implementation was accurate. All done in Verilog with ModelSim. Was a valuable learning experience.