[HIP] Add offload PGO tiled matmul E2E test - #366
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jmmartinez
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jmmartinez
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Looks good to me but I'll JP have the final word.
jplehr
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LG
Just comments about the GPU arch of the bots.
Reporting the actual PGO speed-up just for information purpose is good.
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Gentle ping. The llvm-zorg PR needed by this test has landed now: llvm/llvm-zorg#868 All review comments here have been addressed and resolved. Could you take another look when you get a chance? |
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Add a tiled matrix multiply kernel that demonstrates the offload PGO workflow on AMDGPU. The kernel uses a large per-thread sub-tile (configurable via -DTH_M and -DTH_N) with LDS-based cooperative tile loading, creating natural register pressure that exceeds the VGPR budget and causes spills. Boundary tile handling creates biased branches that PGO can optimize by guiding the register allocator to reduce spills on the hot path. Sub-tile sizes are tunable per architecture to induce spills on GPUs with different register file sizes. Two tests are registered: - pgo-tiled-matmul: correctness test (compile + run + verify) - pgo-tiled-matmul-pipeline: full PGO pipeline test (baseline -> instrument -> collect -> merge -> PGO build -> compare) The pipeline test verifies that the full -fprofile-generate / -fprofile-use workflow completes successfully and reports the performance difference for information.
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@jmmartinez I updated the test so the PGO pipeline only runs when both required profile libraries are available. I also fixed the script so compiler failures are not hidden. Could you please take another look? |
jmmartinez
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The new CMake changes look good to me.
| _hip_profile_rocm_count GREATER 0 AND | ||
| _hip_device_profile_count GREATER 0) |
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Nitpick: In CMake, does an empty list evaluate to false in this context ?
That could allow us to avoid the LENGHT and just check for emptiness of _hip_profile_rocm_count and _hip_device_profile_count
jplehr
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Are there requirements on the installed ROCm version for this to work?
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[HIP] Add offload PGO tiled matmul E2E test
Add a tiled matrix multiply kernel that demonstrates the offload PGO
workflow on AMDGPU. The kernel uses a large per-thread sub-tile
(configurable via -DTH_M and -DTH_N) with LDS-based cooperative tile
loading, creating natural register pressure that exceeds the VGPR
budget and causes spills. Boundary tile handling creates biased
branches that PGO can optimize by guiding the register allocator to
reduce spills on the hot path.
Sub-tile sizes are tunable per architecture to induce spills on GPUs
with different register file sizes.
Two tests are registered:
(baseline -> instrument -> collect -> merge -> PGO build -> compare)
The pipeline test verifies that the full -fprofile-generate /
-fprofile-use workflow completes successfully and reports the
performance difference for information.