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[CIR][CIRGen][Builtin][X86] Lower AVX generic masked store instrinsics #1760

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Merged
merged 1 commit into from
Jul 28, 2025
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[CIR][CIRGen][Builtin][X86] Lower AVX generic masked store instrinsics #1760

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5 changes: 4 additions & 1 deletion clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -568,7 +568,10 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned BuiltinID,
case X86::BI__builtin_ia32_movdqa64store512_mask:
case X86::BI__builtin_ia32_storeaps512_mask:
case X86::BI__builtin_ia32_storeapd512_mask:
llvm_unreachable("vfmaddsubph256_round_mask3 NYI");
return emitX86MaskedStore(
*this, Ops,
getContext().getTypeAlignInChars(E->getArg(1)->getType()).getAsAlign(),
getLoc(E->getExprLoc()));

case X86::BI__builtin_ia32_loadups128_mask:
case X86::BI__builtin_ia32_loadups256_mask:
Expand Down
36 changes: 36 additions & 0 deletions clang/test/CIR/CodeGen/X86/avx512f-builtins.c
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Expand Up @@ -46,3 +46,39 @@ void test_mm_mask_store_sd(double * __P, __mmask8 __U, __m128d __A){
// LLVM: call void @llvm.masked.store.v2f64.p0(<2 x double> %{{.*}}, ptr %{{.*}}, i32 1, <2 x i1> %{{.*}})
_mm_mask_store_sd(__P, __U, __A);
}

void test_mm512_mask_store_pd(void *p, __m512d a, __mmask8 m){
// CIR-LABEL: _mm512_mask_store_pd
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!cir.double x 8>, !cir.ptr<!cir.vector<!cir.double x 8>>, !u32i, !cir.vector<!cir.int<s, 1> x 8>) -> !void

// LLVM-LABEL: test_mm512_mask_store_pd
// LLVM: @llvm.masked.store.v8f64.p0(<8 x double> %{{.*}}, ptr %{{.*}}, i32 64, <8 x i1> %{{.*}})
_mm512_mask_store_pd(p, m, a);
}

void test_mm512_mask_store_epi32(void *__P, __mmask16 __U, __m512i __A) {
// CIR-LABEL: _mm512_mask_store_epi32
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!s32i x 16>, !cir.ptr<!cir.vector<!s32i x 16>>, !u32i, !cir.vector<!cir.int<s, 1> x 16>) -> !void

// LLVM-LABEL: test_mm512_mask_store_epi32
// LLVM: @llvm.masked.store.v16i32.p0(<16 x i32> %{{.*}}, ptr %{{.*}}, i32 64, <16 x i1> %{{.*}})
return _mm512_mask_store_epi32(__P, __U, __A);
}

void test_mm512_mask_store_epi64(void *__P, __mmask8 __U, __m512i __A) {
// CIR-LABEL: _mm512_mask_store_epi64
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!s64i x 8>, !cir.ptr<!cir.vector<!s64i x 8>>, !u32i, !cir.vector<!cir.int<s, 1> x 8>) -> !void

// LLVM-LABEL: test_mm512_mask_store_epi64
// LLVM: @llvm.masked.store.v8i64.p0(<8 x i64> %{{.*}}, ptr %{{.*}}, i32 64, <8 x i1> %{{.*}})
return _mm512_mask_store_epi64(__P, __U, __A);
}

void test_mm512_mask_store_ps(void *p, __m512 a, __mmask16 m){
// CIR-LABEL: _mm512_mask_store_ps
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!cir.float x 16>, !cir.ptr<!cir.vector<!cir.float x 16>>, !u32i, !cir.vector<!cir.int<s, 1> x 16>) -> !void

// LLVM-LABEL: test_mm512_mask_store_ps
// LLVM: @llvm.masked.store.v16f32.p0(<16 x float> %{{.*}}, ptr %{{.*}}, i32 64, <16 x i1> %{{.*}})
_mm512_mask_store_ps(p, m, a);
}
63 changes: 63 additions & 0 deletions clang/test/CIR/CodeGen/X86/avx512vl-builtins.c
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Expand Up @@ -68,3 +68,66 @@ void test_mm256_mask_storeu_ps(void *__P, __mmask8 __U, __m256 __A) {
// LLVM: @llvm.masked.store.v8f32.p0(<8 x float> %{{.*}}, ptr %{{.*}}, i32 1, <8 x i1> %{{.*}})
return _mm256_mask_storeu_ps(__P, __U, __A);
}

void test_mm_mask_store_epi64(void *__P, __mmask8 __U, __m128i __A) {
// CIR-LABEL: _mm_mask_store_epi64
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!s64i x 2>, !cir.ptr<!cir.vector<!s64i x 2>>, !u32i, !cir.vector<!cir.int<s, 1> x 2>) -> !void

// LLVM-LABEL: @test_mm_mask_store_epi64
// LLVM: @llvm.masked.store.v2i64.p0(<2 x i64> %{{.*}}, ptr %{{.*}}, i32 16, <2 x i1> %{{.*}})
return _mm_mask_store_epi64(__P, __U, __A);
}

void test_mm_mask_store_ps(void *__P, __mmask8 __U, __m128 __A) {
// CIR-LABEL: _mm_mask_store_ps
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!cir.float x 4>, !cir.ptr<!cir.vector<!cir.float x 4>>, !u32i, !cir.vector<!cir.int<s, 1> x 4>) -> !void

// LLVM-LABEL: @test_mm_mask_store_ps
// LLVM: @llvm.masked.store.v4f32.p0(<4 x float> %{{.*}}, ptr %{{.*}}, i32 16, <4 x i1> %{{.*}})
return _mm_mask_store_ps(__P, __U, __A);
}

void test_mm_mask_store_pd(void *__P, __mmask8 __U, __m128d __A) {
// CIR-LABEL: _mm_mask_store_pd
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!cir.double x 2>, !cir.ptr<!cir.vector<!cir.double x 2>>, !u32i, !cir.vector<!cir.int<s, 1> x 2>) -> !void

// LLVM-LABEL: @test_mm_mask_store_pd
// LLVM: @llvm.masked.store.v2f64.p0(<2 x double> %{{.*}}, ptr %{{.*}}, i32 16, <2 x i1> %{{.*}})
return _mm_mask_store_pd(__P, __U, __A);
}

void test_mm256_mask_store_epi32(void *__P, __mmask8 __U, __m256i __A) {
// CIR-LABEL: _mm256_mask_store_epi32
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!s32i x 8>, !cir.ptr<!cir.vector<!s32i x 8>>, !u32i, !cir.vector<!cir.int<s, 1> x 8>) -> !void

// LLVM-LABEL: @test_mm256_mask_store_epi32
// LLVM: @llvm.masked.store.v8i32.p0(<8 x i32> %{{.*}}, ptr %{{.*}}, i32 32, <8 x i1> %{{.*}})
return _mm256_mask_store_epi32(__P, __U, __A);
}

void test_mm256_mask_store_epi64(void *__P, __mmask8 __U, __m256i __A) {
// CIR-LABEL: _mm256_mask_store_epi64
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!s64i x 4>, !cir.ptr<!cir.vector<!s64i x 4>>, !u32i, !cir.vector<!cir.int<s, 1> x 4>) -> !void

// LLVM-LABEL: @test_mm256_mask_store_epi64
// LLVM: @llvm.masked.store.v4i64.p0(<4 x i64> %{{.*}}, ptr %{{.*}}, i32 32, <4 x i1> %{{.*}})
return _mm256_mask_store_epi64(__P, __U, __A);
}

void test_mm256_mask_store_ps(void *__P, __mmask8 __U, __m256 __A) {
// CIR-LABEL: _mm256_mask_store_ps
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!cir.float x 8>, !cir.ptr<!cir.vector<!cir.float x 8>>, !u32i, !cir.vector<!cir.int<s, 1> x 8>) -> !void

// LLVM-LABEL: @test_mm256_mask_store_ps
// LLVM: @llvm.masked.store.v8f32.p0(<8 x float> %{{.*}}, ptr %{{.*}}, i32 32, <8 x i1> %{{.*}})
return _mm256_mask_store_ps(__P, __U, __A);
}

void test_mm256_mask_store_pd(void *__P, __mmask8 __U, __m256d __A) {
// CIR-LABEL: _mm256_mask_store_pd
// CIR: %{{.*}} = cir.llvm.intrinsic "masked.store" %{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<!cir.double x 4>, !cir.ptr<!cir.vector<!cir.double x 4>>, !u32i, !cir.vector<!cir.int<s, 1> x 4>) -> !void

// LLVM-LABEL: @test_mm256_mask_store_pd
// LLVM: @llvm.masked.store.v4f64.p0(<4 x double> %{{.*}}, ptr %{{.*}}, i32 32, <4 x i1> %{{.*}})
return _mm256_mask_store_pd(__P, __U, __A);
}
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