Abstract Pio register layout to support more SoC - #251
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August 1, 2026 01:06
The GPIO bank controller has different register layout information among different SoC generations, abstract those info in the driver. Take T153 SoC chip GPIO controller as example 1) base: The BASE address of GPIO controller 17.9.5.1 page-1085 (1115/1759) of datasheet GPIO Base address 0x03604000 2) offs: First GPIO bank offset to GPIO base address, usually it's PA PA_CFG0 - 0x0080 (PA Configure Register 0) Usually it's the PA_CFG0 register offset 3) size: Register space of each GPIO bank, can be caculated from size = (PB_CFG0 - PA_CFG0) = (0x100 - 0x80) = 0x80 4) pull: GPIO PULL register offset to its bank base address PA_PULL0 - 0x00B0 pull = (PA_PULL0 - PA_CFG0) = 0xB0 - 0x80 = 0x30 In the driver, only update SoC which support FLAG_NEW_GPIO to new layout. Signed-off-by: Yixun Lan <dlan@kernel.org>
Update SoC which support FLAG_NCAT2 (FLAG_NEW_GPIO) Signed-off-by: Yixun Lan <dlan@kernel.org>
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This is a prerequisite patch to support T153 SoC, also A733 can be adapted to this new model too.