Analyze and simulate the behavior of a Translation Lookaside Buffer (TLB) in modern memory management systems. This project calculates Effective Memory Access Time (EMAT) through hit/miss rate analysis across different simulation parameters.
In computer architecture, a Translation Lookaside Buffer (TLB) is a memory cache that stores recent translations of virtual memory to physical memory. This project provides a comprehensive simulation environment to:
- Evaluate how TLB size and access patterns affect performance.
- Calculate Effective Memory Access Time (EMAT).
- Visualize performance metrics through a dynamic web interface.
Modern Streamlit-based Web Interface for interactive analysis.
- Deterministic Simulation: Accurate tracking of TLB hits and misses.
- Locality-aware Address Generation: Simulates realistic memory access patterns using a locality-based generator.
- Dynamic Analysis: Adjust Page Size, TLB Size, and Number of Accesses in real-time.
- EMAT Calculation: Integrated performance metric engine.
- Dual Mode: Choose between a command-line interface (CLI) or a full-featured Streamlit Web UI.
The simulation follows a standard memory translation logic:
- Virtual Address Generation: A virtual address is generated (optionally with spatial locality).
- Page Number Extraction: The system extracts the page number derived from the virtual address.
- TLB Lookup:
- Hit: If the page is in the TLB, the physical frame is retrieved instantly.
- Miss: If not in the TLB, the system looks up the Page Table and updates the TLB.
- FIFO Replacement: If the TLB is full, the oldest entry is replaced (First-In, First-Out).
- EMAT Calculation: Based on final Hit/Miss rates, the effective access time is computed.
- Algorithm: FIFO (First-In, First-Out).
- Default Size: 16 slots.
- Logic: Implemented in
simulator.pyusing a list-based queue mechanism.
- A direct mapping project where virtual pages are mapped to physical frames based on a simulated memory footprint.
- Uses a locality-based approach to better simulate real-world software behavior where consecutive memory accesses often fall within the same or nearby pages.
- TLB Access Time: 10 ns
- Main Memory Access Time: 100 ns
- Replacement Policy: FIFO
The Effective Memory Access Time (EMAT) is calculated as:
EMAT = (Hit_Rate * (TLB_Time + Memory_Time)) + ((1 - Hit_Rate) * (TLB_Time + 2 * Memory_Time))
Running main.py provides high-speed simulation results:
===== PERFORMANCE =====
Total Accesses: 1000
TLB Hits: 320
TLB Misses: 680
Hit Rate: 0.32
Miss Rate: 0.68
EMAT: 178.00 ns
# Install dependencies
pip install streamlit pandaspython main.pystreamlit run app.pysimulator.py: Core logic forMemorySimulatorand address translation.main.py: Command-line script for quick performance snapshots.app.py: Streamlit application for interactive visualizations.utils.py: Helper functions for system-level operations.
- LRU Replacement: Implement Least Recently Used policy for comparison.
- Comparative Graphs: Track EMAT changes as TLB size grows.
- Trace Support: Support for real trace files (e.g., Valgrind output).
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