Add benchmarking support for OpenRISC Cores

.gitignore

@@ -15,4 +15,8 @@ __pycache__/
 
 # Default build and log directories
 bd*/
-logs/
+logs*/
+build/
+
+# generated fusesoc libraries
+fusesoc_libraries/

benchmark_speed.py

@@ -359,7 +359,7 @@ def collect_data(benchmarks, args):
     # Baseline data is held external to the script. Import it here if we are
     # doing relative output and then generate the relative data
     if not gp['absolute']:
-        rel_data = compute_rel(benchmarks, raw_data, args)
+        rel_data = compute_rel(benchmarks_run, raw_data, args)
     else:
         rel_data = {}
 

examples/openrisc/fusesoc.conf

@@ -0,0 +1,36 @@
+[library.fusesoc-cores]
+location = fusesoc_libraries/fusesoc-cores
+sync-uri = https://github.com/fusesoc/fusesoc-cores
+sync-type = git
+auto-sync = true
+
+[library.intgen]
+location = fusesoc_libraries/intgen
+sync-uri = https://github.com/stffrdhrn/intgen.git
+sync-type = git
+auto-sync = true
+
+[library.elf-loader]
+location = fusesoc_libraries/elf-loader
+sync-uri = https://github.com/fusesoc/elf-loader.git
+sync-type = git
+auto-sync = true
+
+[library.mor1kx-generic]
+location = fusesoc_libraries/mor1kx-generic
+sync-uri = https://github.com/stffrdhrn/mor1kx-generic.git
+sync-type = git
+auto-sync = true
+
+[library.or1k_marocchino]
+location = fusesoc_libraries/or1k_marocchino
+sync-uri = https://github.com/openrisc/or1k_marocchino.git
+sync-type = git
+auto-sync = true
+
+[library.mor1kx]
+location = fusesoc_libraries/mor1kx
+sync-uri = https://github.com/openrisc/mor1kx.git
+sync-type = git
+auto-sync = true
+

examples/openrisc/maroccino/README.md

@@ -0,0 +1,22 @@
+build command
+
+```bash
+scons --build-dir=bdMaroccino --config-dir=examples/openrisc/maroccino/ user_libs=-lm \
+                                                         cc=or1k-elf-gcc \
+                                                         cflags='-c -O3 -fdata-sections -ffunction-sections -mcmov -mhard-float -mror -mrori -msext -msfimm -mshftimm -munordered-float' \
+                                                         ldflags='-O3 -Wl,-gc-sections'
+```
+
+make sure or1k-elf-gcc is in your PATH, or change the cc variable to point to the correct location of the compiler.
+
+[TODO] Linker is faulty. `linker.ld` includes `generated/output_format.ld` and `generated/regions.ld`, so those files must exist under the selected `--config-dir`-- written by 2024 student.
+
+Command to for benchmark_size
+```bash
+python benchmark_size.py --builddir bdMaroccino/ --logdir logsMaroccino --baselinedir baseline-data/
+```
+
+Command for speed results
+```bash
+python benchmark_speed.py --builddir bdMaroccino/ --logdir logsMaroccino --baselinedir baseline-data/ --target-module run_mor1kx --cpu-mhz 1 --timeout 600 --config-path examples/openrisc/fusesoc.conf --tool verilator --system ::mor1kx-generic:1.1 --fusesoc_target marocchino_tb
+```

examples/openrisc/maroccino/boardsupport.c

@@ -0,0 +1,41 @@
+
+#include <support.h>
+#include <stdio.h>
+#include <or1k-support.h>
+#include <or1k-sprs.h>
+#include <inttypes.h>
+#include <stdint.h>
+
+#define BOARD_CPU_HZ 1000000UL
+
+uint32_t _or1k_board_uart_base = 0x90000000;
+uint32_t _or1k_board_uart_baud = 9600;
+uint32_t _or1k_board_clk_freq = BOARD_CPU_HZ;
+
+static volatile uint32_t start = 0;
+static volatile uint32_t end = 0;
+
+void
+initialise_board ()
+{
+   or1k_timer_init (BOARD_CPU_HZ);
+   /* TTMR[M]=0b11, continuous mode. */
+   or1k_timer_set_mode (3u);
+}
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+start_trigger ()
+{
+   or1k_timer_enable ();
+   start = or1k_mfspr (OR1K_SPR_TICK_TTCR_ADDR);
+}
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+stop_trigger ()
+{
+   uint32_t elapsed;
+
+   end = or1k_mfspr (OR1K_SPR_TICK_TTCR_ADDR);
+   elapsed = end - start;
+   printf ("End time %" PRIu32 "\n", elapsed);
+}

examples/openrisc/maroccino/boardsupport.h

@@ -0,0 +1,3 @@
+
+
+#define CPU_MHZ 1

examples/openrisc/maroccino/linker.ld

@@ -0,0 +1,86 @@
+INCLUDE generated/output_format.ld
+INCLUDE generated/regions.ld
+
+ENTRY(_start)
+
+
+SECTIONS
+{
+	.text :
+	{
+		_ftext = .;
+                /* Make sure crt0 files come first, and they, and the isr */
+                /* don't get disposed of by greedy optimisation */
+                *crt0*(.text)
+                KEEP(*crt0*(.text))
+                KEEP(*(.text.isr))
+
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		_etext = .;
+	} > main_ram
+
+	.rodata : ALIGN(8)
+	{
+		_frodata = .;
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		*(.rodata1)
+		*(.got .got.*)
+		*(.toc .toc.*)
+
+		/* Make sure the file is aligned on disk as well
+		   as in memory; CRC calculation requires that. */
+		FILL(0);
+		. = ALIGN(8);
+		_erodata = .;
+	} > main_ram
+
+	.commands : ALIGN(8)
+	{
+		PROVIDE_HIDDEN (__bios_cmd_start = .);
+		KEEP(*(.bios_cmd))
+		PROVIDE_HIDDEN (__bios_cmd_end = .);
+	} > main_ram 
+
+	.data : ALIGN(8)
+	{
+		_fdata = .;
+		*(.data .data.* .gnu.linkonce.d.*)
+		*(.data1)
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+
+		/* Make sure the file is aligned on disk as well
+		   as in memory; CRC calculation requires that. */
+		FILL(0);
+		. = ALIGN(8);
+		_edata = .;
+	} > main_ram
+
+	.bss : ALIGN(8) SUBALIGN(8)
+	{
+		_fbss = .;
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		*(.scommon)
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(8);
+		_ebss = .;
+		_end = .;
+	} > main_ram
+	. = ALIGN(8);
+	PROVIDE(__heap_start = . );
+
+	/DISCARD/ :
+	{
+		*(.eh_frame)
+		*(.comment)
+	}
+}
+
+PROVIDE(__heap_end = ORIGIN(main_ram) + LENGTH(main_ram));
+
+PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram));
+
+PROVIDE(_fdata_rom = LOADADDR(.data));
+PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));

examples/openrisc/mor1kx/README.md

@@ -0,0 +1,22 @@
+Command to build the benchmarks for the mor1kx configuration:
+
+```bash
+scons --build-dir=bdMor1kx --config-dir=examples/openrisc/mor1kx/ user_libs=-lm \
+                                                         cc=or1k-elf-gcc \
+                                                         cflags='-c -O3 -fdata-sections -ffunction-sections -mcmov -mhard-float -mror -mrori -msext -msfimm -mshftimm -munordered-float' \
+                                                         ldflags='-O3 -Wl,-gc-sections'
+```
+
+make sure or1k-elf-gcc is in your PATH, or change the cc variable to point to the correct location of the compiler.
+
+[TODO] Linker is faulty. `linker.ld` includes `generated/output_format.ld` and `generated/regions.ld`, so those files must exist under the selected `--config-dir`-- written by 2024 student.
+
+Command to for benchmark_size
+```bash
+python benchmark_size.py --builddir bdMor1kx/ --logdir logsMor1kx --baselinedir baseline-data/
+```
+
+command for speed results
+```bash
+python benchmark_speed.py --builddir bdMor1kx/ --logdir logsMor1kx --baselinedir baseline-data/ --target-module run_mor1kx --cpu-mhz 1 --timeout 600 --config-path examples/openrisc/fusesoc.conf --tool verilator --system ::mor1kx-generic:1.1 --fusesoc_target mor1kx_tb
+```

examples/openrisc/mor1kx/boardsupport.c

@@ -0,0 +1,43 @@
+
+
+#include <support.h>
+#include <stdio.h>
+#include <or1k-support.h>
+#include <or1k-sprs.h>
+#include <inttypes.h>
+#include <stdint.h>
+
+#define BOARD_CPU_HZ 1000000UL
+
+uint32_t _or1k_board_uart_base = 0x90000000;
+uint32_t _or1k_board_uart_baud = 9600;
+uint32_t _or1k_board_clk_freq = BOARD_CPU_HZ;
+
+
+static volatile uint32_t start = 0;
+static volatile uint32_t end = 0;
+
+void
+initialise_board ()
+{
+   or1k_timer_init (BOARD_CPU_HZ);
+   /* TTMR[M]=0b11, continuous mode. */
+   or1k_timer_set_mode (3u);
+}
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+start_trigger ()
+{
+   or1k_timer_enable ();
+   start = or1k_mfspr (OR1K_SPR_TICK_TTCR_ADDR);
+}
+
+void __attribute__ ((noinline)) __attribute__ ((externally_visible))
+stop_trigger ()
+{
+   uint32_t elapsed;
+
+   end = or1k_mfspr (OR1K_SPR_TICK_TTCR_ADDR);
+   elapsed = end - start;
+   printf ("End time %" PRIu32 "\n", elapsed);
+}

examples/openrisc/mor1kx/boardsupport.h

@@ -0,0 +1,3 @@
+
+
+#define CPU_MHZ 1

examples/openrisc/mor1kx/linker.ld

@@ -0,0 +1,86 @@
+INCLUDE generated/output_format.ld
+INCLUDE generated/regions.ld
+
+ENTRY(_start)
+
+
+SECTIONS
+{
+	.text :
+	{
+		_ftext = .;
+                /* Make sure crt0 files come first, and they, and the isr */
+                /* don't get disposed of by greedy optimisation */
+                *crt0*(.text)
+                KEEP(*crt0*(.text))
+                KEEP(*(.text.isr))
+
+		*(.text .stub .text.* .gnu.linkonce.t.*)
+		_etext = .;
+	} > main_ram
+
+	.rodata : ALIGN(8)
+	{
+		_frodata = .;
+		*(.rodata .rodata.* .gnu.linkonce.r.*)
+		*(.rodata1)
+		*(.got .got.*)
+		*(.toc .toc.*)
+
+		/* Make sure the file is aligned on disk as well
+		   as in memory; CRC calculation requires that. */
+		FILL(0);
+		. = ALIGN(8);
+		_erodata = .;
+	} > main_ram
+
+	.commands : ALIGN(8)
+	{
+		PROVIDE_HIDDEN (__bios_cmd_start = .);
+		KEEP(*(.bios_cmd))
+		PROVIDE_HIDDEN (__bios_cmd_end = .);
+	} > main_ram 
+
+	.data : ALIGN(8)
+	{
+		_fdata = .;
+		*(.data .data.* .gnu.linkonce.d.*)
+		*(.data1)
+		*(.sdata .sdata.* .gnu.linkonce.s.*)
+
+		/* Make sure the file is aligned on disk as well
+		   as in memory; CRC calculation requires that. */
+		FILL(0);
+		. = ALIGN(8);
+		_edata = .;
+	} > main_ram
+
+	.bss : ALIGN(8) SUBALIGN(8)
+	{
+		_fbss = .;
+		*(.dynsbss)
+		*(.sbss .sbss.* .gnu.linkonce.sb.*)
+		*(.scommon)
+		*(.dynbss)
+		*(.bss .bss.* .gnu.linkonce.b.*)
+		*(COMMON)
+		. = ALIGN(8);
+		_ebss = .;
+		_end = .;
+	} > main_ram
+	. = ALIGN(8);
+	PROVIDE(__heap_start = . );
+
+	/DISCARD/ :
+	{
+		*(.eh_frame)
+		*(.comment)
+	}
+}
+
+PROVIDE(__heap_end = ORIGIN(main_ram) + LENGTH(main_ram));
+
+PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram));
+
+PROVIDE(_fdata_rom = LOADADDR(.data));
+PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));