[wasm] Implement RelaxedSimd intrinsics api

eng/native.wasm.targets

@@ -56,12 +56,14 @@
     <BrowserHostInvariantGlobalization Condition="'$(BrowserHostInvariantGlobalization)' == ''">false</BrowserHostInvariantGlobalization>
     <BrowserHostInvariantTimezone Condition="'$(BrowserHostInvariantTimezone)' == ''">false</BrowserHostInvariantTimezone>
     <BrowserHostEnableDiagnostics Condition="'$(BrowserHostEnableDiagnostics)' == ''">false</BrowserHostEnableDiagnostics>
+    <BrowserHostEnableRelaxedSimd Condition="'$(BrowserHostEnableRelaxedSimd)' == ''">false</BrowserHostEnableRelaxedSimd>
   </PropertyGroup>
 
   <ItemGroup Condition="'$(TargetsBrowser)' == 'true' and '$(RuntimeFlavor)' == 'CoreCLR'">
     <_CoreCLRPropertyThatTriggersRelinking Include="InvariantGlobalization" RuntimePackValue="$(BrowserHostInvariantGlobalization)" />
     <_CoreCLRPropertyThatTriggersRelinking Include="InvariantTimezone" RuntimePackValue="$(BrowserHostInvariantTimezone)" />
     <_CoreCLRPropertyThatTriggersRelinking Include="EnableDiagnostics" RuntimePackValue="$(BrowserHostEnableDiagnostics)" />
+    <_CoreCLRPropertyThatTriggersRelinking Include="WasmEnableRelaxedSimd" RuntimePackValue="$(BrowserHostEnableRelaxedSimd)" />
     <_CoreCLRPropertyThatTriggersRelinking Include="WasmInitialHeapSize" RuntimePackValue="$(BrowserHostInitialHeapSize)" />
     <_CoreCLRPropertyThatTriggersRelinking Include="EmccMaximumHeapSize" RuntimePackValue="$(BrowserHostMaximumHeapSize)" />
     <_CoreCLRPropertyThatTriggersRelinking Include="EmccStackSize" RuntimePackValue="$(BrowserHostStackSize)" />

eng/pipelines/coreclr/hardware-intrinsics-wasm.yml

@@ -28,4 +28,4 @@ extends:
         parameters:
           platforms:
             - browser_wasm
-          testBuildArgs: '/p:EnableWasmHWIntrinsicsTests=true -tree:JIT/HardwareIntrinsics/Wasm'
+          testBuildArgs: '/p:EnableWasmHWIntrinsicsTests=true /p:WasmEnableRelaxedSimd=true -tree:JIT/HardwareIntrinsics/Wasm'

eng/pipelines/runtime.yml

@@ -1251,7 +1251,7 @@ extends:
           runOnlyOnChromeVersionUpdate: true
           shouldRunSmokeOnly: 'true'
           nameSuffix: _SmokeMac
-          extraBuildArgs: /p:AotHostArchitecture=arm64 /p:AotHostOS=$(_hostedOS)
+          extraBuildArgs: /p:AotHostArchitecture=x64 /p:AotHostOS=$(_hostedOS)
           useHelixMonitor: ${{ variables.enableHelixJobMonitor }}
           scenarios:
             - WasmTestOnChrome

eng/testing/BrowserVersions.props

@@ -12,9 +12,9 @@
     <win_ChromeRevision>1681091</win_ChromeRevision>
     <win_ChromeBaseSnapshotUrl>https://storage.googleapis.com/chromium-browser-snapshots/Win_x64/1681099</win_ChromeBaseSnapshotUrl>
     <win_V8Version>15.3.76</win_V8Version>
-    <linux_FirefoxRevision>140.11.0esr</linux_FirefoxRevision>
+    <linux_FirefoxRevision>155.0.1</linux_FirefoxRevision>
     <linux_GeckoDriverRevision>0.37.0</linux_GeckoDriverRevision>
-    <win_FirefoxRevision>140.11.0esr</win_FirefoxRevision>
+    <win_FirefoxRevision>155.0.1</win_FirefoxRevision>
     <win_GeckoDriverRevision>0.37.0</win_GeckoDriverRevision>
   </PropertyGroup>
 </Project>

eng/testing/tests.wasm.targets

@@ -89,12 +89,16 @@
       -->
     <_WasmIntrinsicsSubstitutions Condition="'$(WasmEnableSIMD)' != 'false'">WasmIntrinsics</_WasmIntrinsicsSubstitutions>
     <_WasmIntrinsicsSubstitutions Condition="'$(WasmEnableSIMD)' == 'false'">NoWasmIntrinsics</_WasmIntrinsicsSubstitutions>
+    <_WasmRelaxedSimdSubstitutions Condition="'$(WasmEnableSIMD)' != 'false' and '$(WasmEnableRelaxedSimd)' == 'true'">WasmRelaxedSimd</_WasmRelaxedSimdSubstitutions>
+    <_WasmRelaxedSimdSubstitutions Condition="'$(WasmEnableSIMD)' != 'false' and '$(WasmEnableRelaxedSimd)' != 'true'">NoWasmRelaxedSimd</_WasmRelaxedSimdSubstitutions>
     <!-- WasmEnableSIMD is about native codegen, and CoreCLR browser-wasm forces it on, but the CoreCLR
          interpreter maps every System.Runtime.Intrinsics arch intrinsic except get_IsSupported to
          PlatformNotSupportedException. Only crossgen'd code can execute them, so without ReadyToRun stubbing
          IsSupported to true leaves a guarded SIMD path unconditionally reachable and it throws at startup. -->
     <_WasmIntrinsicsSubstitutions Condition="'$(RuntimeFlavor)' == 'CoreCLR' and '$(PublishReadyToRun)' != 'true'">NoWasmIntrinsics</_WasmIntrinsicsSubstitutions>
+    <_WasmRelaxedSimdSubstitutions Condition="'$(RuntimeFlavor)' == 'CoreCLR' and '$(PublishReadyToRun)' != 'true'"></_WasmRelaxedSimdSubstitutions>
     <_ExtraTrimmerArgs>$(_ExtraTrimmerArgs) --substitutions "$(BrowserProjectRoot)build\ILLink.Substitutions.$(_WasmIntrinsicsSubstitutions).xml"</_ExtraTrimmerArgs>
+    <_ExtraTrimmerArgs Condition="'$(_WasmRelaxedSimdSubstitutions)' != ''">$(_ExtraTrimmerArgs) --substitutions "$(BrowserProjectRoot)build\ILLink.Substitutions.$(_WasmRelaxedSimdSubstitutions).xml"</_ExtraTrimmerArgs>
   </PropertyGroup>
 
   <ItemGroup>
@@ -165,6 +169,7 @@
       <_WasmPropertyNames Include="WasmBuildNative" />
       <_WasmPropertyNames Include="WasmDebugLevel" />
       <_WasmPropertyNames Include="WasmDedup" />
+      <_WasmPropertyNames Include="WasmEnableRelaxedSimd" />
       <_WasmPropertyNames Include="WasmLinkIcalls" />
       <_WasmPropertyNames Include="WasmNativeStrip" />
       <_WasmPropertyNames Include="WasmNativeDebugSymbols" />

src/coreclr/inc/corinfoinstructionset.h

@@ -70,6 +70,7 @@ enum CORINFO_InstructionSet
     InstructionSet_WasmBase=1,
     InstructionSet_PackedSimd=2,
     InstructionSet_Vector128=3,
+    InstructionSet_RelaxedSimd=4,
 #endif // TARGET_WASM
 #ifdef TARGET_AMD64
     InstructionSet_X86Base=1,
@@ -473,6 +474,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
 #ifdef TARGET_WASM
         if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_PackedSimd))
             resultflags.RemoveInstructionSet(InstructionSet_Vector128);
+        if (resultflags.HasInstructionSet(InstructionSet_RelaxedSimd) && !resultflags.HasInstructionSet(InstructionSet_PackedSimd))
+            resultflags.RemoveInstructionSet(InstructionSet_RelaxedSimd);
         if (resultflags.HasInstructionSet(InstructionSet_PackedSimd) && !resultflags.HasInstructionSet(InstructionSet_WasmBase))
             resultflags.RemoveInstructionSet(InstructionSet_PackedSimd);
 #endif // TARGET_WASM
@@ -785,6 +788,8 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
             return "PackedSimd";
         case InstructionSet_Vector128 :
             return "Vector128";
+        case InstructionSet_RelaxedSimd :
+            return "RelaxedSimd";
 #endif // TARGET_WASM
 #ifdef TARGET_AMD64
         case InstructionSet_X86Base :
@@ -993,6 +998,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
 #ifdef TARGET_WASM
         case READYTORUN_INSTRUCTION_WasmBase: return InstructionSet_WasmBase;
         case READYTORUN_INSTRUCTION_PackedSimd: return InstructionSet_PackedSimd;
+        case READYTORUN_INSTRUCTION_RelaxedSimd: return InstructionSet_RelaxedSimd;
 #endif // TARGET_WASM
 #ifdef TARGET_AMD64
         case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;

src/coreclr/inc/jiteeversionguid.h

@@ -37,11 +37,11 @@
 
 #include <minipal/guid.h>
 
-constexpr GUID JITEEVersionIdentifier = { /* 5a3e8dc8-83bf-47e5-b032-531dbd307dbe */
-    0x5a3e8dc8,
-    0x83bf,
-    0x47e5,
-    {0xb0, 0x32, 0x53, 0x1d, 0xbd, 0x30, 0x7d, 0xbe}
+constexpr GUID JITEEVersionIdentifier = { /* d663060e-9184-48cb-b7dc-c8afa4b33a82 */
+    0xd663060e,
+    0x9184,
+    0x48cb,
+    {0xb7, 0xdc, 0xc8, 0xaf, 0xa4, 0xb3, 0x3a, 0x82}
   };
 
 #endif // JIT_EE_VERSIONING_GUID_H

src/coreclr/inc/readytoruninstructionset.h

@@ -103,6 +103,7 @@ enum ReadyToRunInstructionSet
     READYTORUN_INSTRUCTION_Cssc=93,
     READYTORUN_INSTRUCTION_Zicond=94,
     READYTORUN_INSTRUCTION_Fp16=95,
+    READYTORUN_INSTRUCTION_RelaxedSimd=96,
 
 };
 

src/coreclr/jit/hwintrinsic.cpp

@@ -1019,6 +1019,7 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
     { FIRST_NI_WasmBase, LAST_NI_WasmBase },                    // WasmBase
     { FIRST_NI_PackedSimd, LAST_NI_PackedSimd },                // PackedSimd
     { FIRST_NI_Vector, LAST_NI_Vector },                        // Vector128
+    { FIRST_NI_RelaxedSimd, LAST_NI_RelaxedSimd },              // RelaxedSimd
 #else
 #error Unsupported platform
 #endif

src/coreclr/jit/hwintrinsiclistwasm.h

@@ -82,6 +82,21 @@ HARDWARE_INTRINSIC(PackedSimd,      ZeroExtendWideningLower,
 HARDWARE_INTRINSIC(PackedSimd,      ZeroExtendWideningUpper,                                         16,              1,     INS_i16x8_extend_high_u_i8x16,        INS_i16x8_extend_high_u_i8x16,        INS_i32x4_extend_high_u_i16x8,        INS_i32x4_extend_high_u_i16x8,        INS_i64x2_extend_high_u_i32x4,    INS_i64x2_extend_high_u_i32x4,    INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
 #define LAST_NI_PackedSimd NI_PackedSimd_ZeroExtendWideningUpper
 
+//  RelaxedSimd Intrinsics
+#define FIRST_NI_RelaxedSimd        NI_RelaxedSimd_ConvertToInt32Native
+HARDWARE_INTRINSIC(RelaxedSimd,     ConvertToInt32Native,                                            16,              1,     INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_i32x4_relaxed_trunc_f32x4_s,      INS_i32x4_relaxed_trunc_f64x2_s_zero, -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(RelaxedSimd,     ConvertToUInt32Native,                                           16,              1,     INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_i32x4_relaxed_trunc_f32x4_u,      INS_i32x4_relaxed_trunc_f64x2_u_zero, -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(RelaxedSimd,     DotProductAddNative,                                             16,              3,     INS_i32x4_relaxed_dot_i8x16_i7x16_add_s, INS_invalid,                       INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(RelaxedSimd,     DotProductNative,                                                16,              2,     INS_i16x8_relaxed_dot_i8x16_i7x16_s,  INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(RelaxedSimd,     LaneSelectNative,                                                16,              3,     INS_i8x16_relaxed_laneselect,         INS_i8x16_relaxed_laneselect,         INS_i16x8_relaxed_laneselect,         INS_i16x8_relaxed_laneselect,         INS_i32x4_relaxed_laneselect,     INS_i32x4_relaxed_laneselect,     INS_i64x2_relaxed_laneselect,         INS_i64x2_relaxed_laneselect,         INS_invalid,                          INS_invalid,                          -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(RelaxedSimd,     MaxNative,                                                       16,              2,     INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_f32x4_relaxed_max,                INS_f64x2_relaxed_max,                -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg|HW_Flag_Commutative)
+HARDWARE_INTRINSIC(RelaxedSimd,     MinNative,                                                       16,              2,     INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_f32x4_relaxed_min,                INS_f64x2_relaxed_min,                -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg|HW_Flag_Commutative)
+HARDWARE_INTRINSIC(RelaxedSimd,     MultiplyAddEstimate,                                             16,              3,     INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_f32x4_relaxed_madd,               INS_f64x2_relaxed_madd,               -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(RelaxedSimd,     MultiplyAddNegatedEstimate,                                      16,              3,     INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_f32x4_relaxed_nmadd,              INS_f64x2_relaxed_nmadd,              -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+HARDWARE_INTRINSIC(RelaxedSimd,     MultiplyRoundedQ15Native,                                        16,              2,     INS_invalid,                          INS_invalid,                          INS_i16x8_relaxed_q15mulr_s,          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg|HW_Flag_Commutative)
+HARDWARE_INTRINSIC(RelaxedSimd,     SwizzleNative,                                                   16,              2,     INS_i8x16_relaxed_swizzle,            INS_i8x16_relaxed_swizzle,            INS_invalid,                          INS_invalid,                          INS_invalid,                      INS_invalid,                      INS_invalid,                          INS_invalid,                          INS_invalid,                          INS_invalid,                          -1,        -1,         HW_Category_SIMD,                   HW_Flag_BaseTypeFromFirstArg)
+#define LAST_NI_RelaxedSimd NI_RelaxedSimd_SwizzleNative
+
 //  WasmBase Intrinsics
 //  These scalar intrinsics are special-imported (see hwintrinsicwasm.cpp) and always rewritten into the
 //  existing NI_PRIMITIVE_*ZeroCount GT_INTRINSIC nodes (which codegen already emits as wasm clz/ctz), so

src/coreclr/jit/hwintrinsicwasm.cpp

@@ -25,6 +25,10 @@ CORINFO_InstructionSet Compiler::lookupInstructionSet(const char* className)
     {
         return InstructionSet_PackedSimd;
     }
+    else if (strcmp(className, "RelaxedSimd") == 0)
+    {
+        return InstructionSet_RelaxedSimd;
+    }
     else if ((strcmp(className, "Vector128") == 0) || (strcmp(className, "Vector128`1") == 0))
     {
         return InstructionSet_Vector128;

src/coreclr/jit/instrswasm.h

@@ -527,6 +527,28 @@ INST2(i32x4_trunc_sat_u_f64x2_zero,   "i32x4.trunc_sat_u_f64x2_zero",   0, IF_OP
 INST2(f64x2_convert_low_s_i32x4,      "f64x2.convert_low_s_i32x4",      0, IF_OPCODE, 0xFD, 254)
 INST2(f64x2_convert_low_u_i32x4,      "f64x2.convert_low_u_i32x4",      0, IF_OPCODE, 0xFD, 255)
 
+// Relaxed SIMD operations
+INST2(i8x16_relaxed_swizzle,                   "i8x16.relaxed_swizzle",                   0, IF_OPCODE, 0xFD, 0x100)
+INST2(i32x4_relaxed_trunc_f32x4_s,             "i32x4.relaxed_trunc_f32x4_s",             0, IF_OPCODE, 0xFD, 0x101)
+INST2(i32x4_relaxed_trunc_f32x4_u,             "i32x4.relaxed_trunc_f32x4_u",             0, IF_OPCODE, 0xFD, 0x102)
+INST2(i32x4_relaxed_trunc_f64x2_s_zero,        "i32x4.relaxed_trunc_f64x2_s_zero",        0, IF_OPCODE, 0xFD, 0x103)
+INST2(i32x4_relaxed_trunc_f64x2_u_zero,        "i32x4.relaxed_trunc_f64x2_u_zero",        0, IF_OPCODE, 0xFD, 0x104)
+INST2(f32x4_relaxed_madd,                      "f32x4.relaxed_madd",                      0, IF_OPCODE, 0xFD, 0x105)
+INST2(f32x4_relaxed_nmadd,                     "f32x4.relaxed_nmadd",                     0, IF_OPCODE, 0xFD, 0x106)
+INST2(f64x2_relaxed_madd,                      "f64x2.relaxed_madd",                      0, IF_OPCODE, 0xFD, 0x107)
+INST2(f64x2_relaxed_nmadd,                     "f64x2.relaxed_nmadd",                     0, IF_OPCODE, 0xFD, 0x108)
+INST2(i8x16_relaxed_laneselect,                "i8x16.relaxed_laneselect",                0, IF_OPCODE, 0xFD, 0x109)
+INST2(i16x8_relaxed_laneselect,                "i16x8.relaxed_laneselect",                0, IF_OPCODE, 0xFD, 0x10A)
+INST2(i32x4_relaxed_laneselect,                "i32x4.relaxed_laneselect",                0, IF_OPCODE, 0xFD, 0x10B)
+INST2(i64x2_relaxed_laneselect,                "i64x2.relaxed_laneselect",                0, IF_OPCODE, 0xFD, 0x10C)
+INST2(f32x4_relaxed_min,                       "f32x4.relaxed_min",                       0, IF_OPCODE, 0xFD, 0x10D)
+INST2(f32x4_relaxed_max,                       "f32x4.relaxed_max",                       0, IF_OPCODE, 0xFD, 0x10E)
+INST2(f64x2_relaxed_min,                       "f64x2.relaxed_min",                       0, IF_OPCODE, 0xFD, 0x10F)
+INST2(f64x2_relaxed_max,                       "f64x2.relaxed_max",                       0, IF_OPCODE, 0xFD, 0x110)
+INST2(i16x8_relaxed_q15mulr_s,                 "i16x8.relaxed_q15mulr_s",                 0, IF_OPCODE, 0xFD, 0x111)
+INST2(i16x8_relaxed_dot_i8x16_i7x16_s,         "i16x8.relaxed_dot_i8x16_i7x16_s",         0, IF_OPCODE, 0xFD, 0x112)
+INST2(i32x4_relaxed_dot_i8x16_i7x16_add_s,     "i32x4.relaxed_dot_i8x16_i7x16_add_s",     0, IF_OPCODE, 0xFD, 0x113)
+
 // clang-format on
 
 #undef INST

src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs

@@ -106,5 +106,6 @@ public enum ReadyToRunInstructionSet
         Cssc = 93,
         Zicond = 94,
         Fp16 = 95,
+        RelaxedSimd = 96,
     }
 }

src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs

@@ -89,6 +89,7 @@ public static class ReadyToRunInstructionSetHelper
                         case InstructionSet.Wasm32_WasmBase: return ReadyToRunInstructionSet.WasmBase;
                         case InstructionSet.Wasm32_PackedSimd: return ReadyToRunInstructionSet.PackedSimd;
                         case InstructionSet.Wasm32_Vector128: return null;
+                        case InstructionSet.Wasm32_RelaxedSimd: return ReadyToRunInstructionSet.RelaxedSimd;
 
                         default: throw new Exception("Unknown instruction set");
                     }