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cd25af8
Porting over from cryspen-ext/core-models:simd-debug
satiscugcat Jun 30, 2025
f138cb8
Removing no_models
satiscugcat Jun 30, 2025
c72c1ca
Removed fstar things
satiscugcat Jul 4, 2025
e72512f
Removing hax dependencies
satiscugcat Jul 9, 2025
5dc77bc
Formatting
satiscugcat Jul 9, 2025
34fad17
More axing the hax
satiscugcat Jul 9, 2025
8ded4c5
Moving int_vec_interp
satiscugcat Jul 9, 2025
1607c83
Finished moving things, should be alright now!
satiscugcat Jul 9, 2025
fae168d
Formatting
satiscugcat Jul 9, 2025
178531a
Update testable-simd-models/src/core_arch/arm_shared/models/mod.rs
satiscugcat Jul 10, 2025
2c7db29
Update testable-simd-models/src/core_arch/x86/models/mod.rs
satiscugcat Jul 10, 2025
d5650f2
Update testable-simd-models/src/core_arch/x86/tests/avx2.rs
satiscugcat Jul 10, 2025
e25e336
Update testable-simd-models/src/core_arch/x86/tests/avx.rs
satiscugcat Jul 10, 2025
66d89c7
Update testable-simd-models/src/core_arch/x86/tests/sse2.rs
satiscugcat Jul 10, 2025
af40445
Update testable-simd-models/src/core_arch/x86/tests/ssse3.rs
satiscugcat Jul 10, 2025
90e1550
Update testable-simd-models/src/core_arch/arm_shared/models/mod.rs
satiscugcat Jul 10, 2025
88f870e
Update testable-simd-models/src/core_arch/arm_shared/specs/mod.rs
satiscugcat Jul 10, 2025
9397eb4
Update testable-simd-models/src/core_arch/arm_shared/specs/mod.rs
satiscugcat Jul 10, 2025
aaadf27
Update testable-simd-models/src/core_arch/x86/models/mod.rs
satiscugcat Jul 10, 2025
aa9bd4b
Update testable-simd-models/src/core_arch/x86/models/mod.rs
satiscugcat Jul 10, 2025
2c685c4
Update testable-simd-models/src/core_arch/x86/specs/mod.rs
satiscugcat Jul 10, 2025
3b629bd
Update testable-simd-models/src/abstractions/mod.rs
satiscugcat Jul 10, 2025
af49b73
Update testable-simd-models/src/core_arch/arm_shared/models/mod.rs
satiscugcat Jul 10, 2025
412e11c
Update testable-simd-models/src/core_arch/arm_shared/tests/neon.rs
satiscugcat Jul 10, 2025
c6e921c
Documentation changes
satiscugcat Jul 10, 2025
a8458fa
Adding avx tests
satiscugcat Jul 10, 2025
f05c320
Moving an intrinsic to the right place
satiscugcat Jul 13, 2025
be022bd
File left out from last commit
satiscugcat Jul 13, 2025
307d8be
Upgrading to earliest nightly that includes our fix
satiscugcat Jul 13, 2025
ee1e273
Doc updates
satiscugcat Jul 13, 2025
511b4a2
Update testable-simd-models/src/core_arch/x86/models/sse2.rs
satiscugcat Jul 15, 2025
f7ac042
Update testable-simd-models/src/core_arch/x86/models/sse2.rs
satiscugcat Jul 15, 2025
63c0d92
Import fix
satiscugcat Jul 16, 2025
51d28c8
Added missing tests
satiscugcat Jul 16, 2025
b5ee135
updating README
satiscugcat Jul 16, 2025
fb5b397
Fixing spec
satiscugcat Jul 16, 2025
69189c2
Formatting
satiscugcat Jul 16, 2025
428fd3c
edits
karthikbhargavan Jul 22, 2025
1f4b817
Merge branch 'main' into simd-models
karthikbhargavan Jul 25, 2025
d69c8d1
README
karthikbhargavan Jul 25, 2025
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1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -56,3 +56,4 @@ goto-transcoder
# already existing elements were commented out

#/target
testable-simd-models/target
16 changes: 16 additions & 0 deletions testable-simd-models/Cargo.toml
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[package]
name = "testable-simd-models"
version = "0.0.2"
authors = ["Cryspen"]
license = "Apache-2.0"
homepage = "https://github.com/cryspen/verify-rust-std/testable-simd-models"
edition = "2021"
repository = "https://github.com/cryspen/verify-rust-std/testable-simd-models"
readme = "README.md"

[dependencies]
rand = "0.9"
pastey = "0.1.0"

[lints.rust]
unexpected_cfgs = { level = "warn" }
127 changes: 127 additions & 0 deletions testable-simd-models/README.md
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# testable-simd-models
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The README looks good to me, it is clear and concise. The example takes a lot of space though, mostly because of the enumeration of masks. Maybe we could shorten it, for example cutting the middle values for the masks and adding a ...


This crate contains executable, independently testable specifications
for the SIMD intrinsics provided by the `core::arch` library in Rust.
The structure of this crate is based on [rust-lang/stdarch/crates/core_arch](https://github.com/rust-lang/stdarch/tree/master/crates/core_arch).

## Code Structure
Within the `core_arch` folder in this crate, there is a different
folder for each architecture for which we have wrtten models.
In particular, it contains folders for `x86` and `arm_shared`.
Each such folder has 3 sub-folders, `models`, `tests`, and `specs`.

The `models` folder contains the models of the intrinsics, with a file
corresponding to different target features, and are written using the
various abstractions implementedin `crate::abstractions`, especially
those in `crate::abstractions::simd`. These models are meant to
closely resemble their implementations within the Rust core itself.

The `tests` folder contains the tests of these models, and is
structured the same way as `models`. Each file additionally contains
the definition of a macro that makes writing these tests easier. The
tests work by testing the models against the intrinsics in the Rust
core, trying out random inputs (generally 1000), and comparing their
outputs.

## Modeling Process
The process of adding a specific intrinsic's model goes as follows.
For this example, let us say the intrinsic we are adding is
`_mm256_bsrli_epi128` from the avx2 feature set.

1. We go to [rust-lang/stdarch/crates/core_arch/src/x86/](https://github.com/rust-lang/stdarch/tree/master/crates/core_arch/src/x86/), and find the implementation of the intrinsic in `avx2.rs`.

2. We see that the implementation looks like this:
``` rust
/// Shifts 128-bit lanes in `a` right by `imm8` bytes while shifting in zeros.
///
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_bsrli_epi128)
#[inline]
#[target_feature(enable = "avx2")]
#[cfg_attr(test, assert_instr(vpsrldq, IMM8 = 1))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "simd_x86", since = "1.27.0")]
pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
static_assert_uimm_bits!(IMM8, 8);
const fn mask(shift: i32, i: u32) -> u32 {
let shift = shift as u32 & 0xff;
if shift > 15 || (15 - (i % 16)) < shift {
0
} else {
32 + (i + shift)
}
}
unsafe {
let a = a.as_i8x32();
let r: i8x32 = simd_shuffle!(
i8x32::ZERO,
a,
[
mask(IMM8, 0),
mask(IMM8, 1),
mask(IMM8, 2),
mask(IMM8, 3),
...
mask(IMM8, 31),
],
);
transmute(r)
}
}
```
Thus, we then go to to `core_arch/x86/models/avx2.rs`, and add the implementation. After some modification, it ends up looking like this.
``` rust
/// Shifts 128-bit lanes in `a` right by `imm8` bytes while shifting in zeros.
///
/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_bsrli_epi128)

pub fn _mm256_bsrli_epi128<const IMM8: i32>(a: __m256i) -> __m256i {
const fn mask(shift: i32, i: u32) -> u64 {
let shift = shift as u32 & 0xff;
if shift > 15 || (15 - (i % 16)) < shift {
0 as u64
} else {
(32 + (i + shift)) as u64
}
}

let a = BitVec::to_i8x32(a);
let r: i8x32 = simd_shuffle(
i8x32::from_fn(|_| 0),
a,
[
mask(IMM8, 0),
mask(IMM8, 1),
mask(IMM8, 2),
mask(IMM8, 3),
...
mask(IMM8, 31),
],
);
r.into()
}
```

3. Next, we add a test for this intrinsic. For this, we navigate to `core_arch/avx2/tests/avx2.rs`. Since the value of
`IMM8` can be up to 8 bits, we want to test constant arguments up to 255. Thus, we write the following macro invocation.
```rust
mk!([100]_mm256_bsrli_epi128{<0>,<1>,<2>,<3>,...,<255>}(a: BitVec));
```
Here, the `[100]` means we test 100 random inputs for each constant value. This concludes the necessary steps for implementing an intrinsic.


## Contributing Models

To contribute new models of intrinsics, we expect the author to follow
the above steps and provide comprehensive tests. It is important that
the model author look carefully at both the Intel/ARM specification
and the Rust `stdarch` implementation, because the Rust implementation
may not necessarily be correct.

Indeed, the previous implementation of `_mm256_bsrli_epi128` (and a
similar intrinsic called `_mm512_bsrli_epi128`) in `stdarch` had a
bug, which we found during the process of modeling and testing this
intrinsic. This bug was [reported by
us](https://github.com/rust-lang/stdarch/issues/1822) using a failing
test case generated from the testable model and then fixed by [our
PR](https://github.com/rust-lang/stdarch/pull/1823) in the 2025-06-30
version of `stdarch`.
204 changes: 204 additions & 0 deletions testable-simd-models/src/abstractions/bit.rs
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//! # Bit Manipulation and Machine Integer Utilities
//!
//! This module provides utilities for working with individual bits and machine integer types.
//! It defines a [`Bit`] enum to represent a single bit (`0` or `1`) along with convenient
//! conversion implementations between `Bit`, [`bool`], and various primitive integer types.
//!
//! In addition, the module introduces the [`MachineInteger`] trait which abstracts over
//! integer types, providing associated constants:
//!
//! - `BITS`: The size of the integer type in bits.
//! - `SIGNED`: A flag indicating whether the type is signed.
//!
//! The [`Bit`] type includes methods for extracting the value of a specific bit from an integer.
//! For example, [`Bit::of_int`] returns the bit at a given position for a provided integer,
//! handling both positive and negative values (assuming a two's complement representation).
//!
//! # Examples
//!
//! ```rust
//! use testable_simd_models::abstractions::bit::{Bit, MachineInteger};
//!
//! // Extract the 3rd bit (0-indexed) from an integer.
//! let bit = Bit::of_int(42, 2);
//! println!("The extracted bit is: {:?}", bit);
//!
//! // Convert Bit to a primitive integer type.
//! let num: u8 = bit.into();
//! println!("As an integer: {}", num);
//! ```
//!
//! [`bool`]: https://doc.rust-lang.org/std/primitive.bool.html
//! [`Bit::of_int`]: enum.Bit.html#method.of_int

/// Represent a bit: `0` or `1`.
#[derive(Copy, Clone, Eq, PartialEq, Debug)]
pub enum Bit {
Zero,
One,
}
impl std::ops::BitAnd for Bit {
type Output = Self;
fn bitand(self, rhs: Self) -> Self {
match self {
Bit::Zero => Bit::Zero,
Bit::One => rhs,
}
}
}

impl std::ops::BitOr for Bit {
type Output = Self;
fn bitor(self, rhs: Self) -> Self {
match self {
Bit::Zero => rhs,
Bit::One => Bit::One,
}
}
}

impl std::ops::BitXor for Bit {
type Output = Self;
fn bitxor(self, rhs: Self) -> Self {
match (self, rhs) {
(Bit::Zero, Bit::Zero) => Bit::Zero,
(Bit::One, Bit::One) => Bit::Zero,
_ => Bit::One,
}
}
}

impl std::ops::Neg for Bit {
type Output = Self;
fn neg(self) -> Self {
match self {
Bit::One => Bit::Zero,
Bit::Zero => Bit::One,
}
}
}
macro_rules! generate_from_bit_impls {
($($ty:ident),*) => {
$(impl From<Bit> for $ty {
fn from(bit: Bit) -> Self {
bool::from(bit) as $ty
}
})*
};
}
generate_from_bit_impls!(u8, u16, u32, u64, u128, i8, i16, i32, i64, i128);

impl From<Bit> for bool {
fn from(bit: Bit) -> Self {
match bit {
Bit::Zero => false,
Bit::One => true,
}
}
}

impl From<bool> for Bit {
fn from(b: bool) -> Bit {
match b {
false => Bit::Zero,
true => Bit::One,
}
}
}

/// A trait for types that represent machine integers.
pub trait MachineInteger {
/// The size of this integer type in bits.
fn bits() -> u32;

/// The signedness of this integer type.
const SIGNED: bool;
/// Element of the integer type with every bit as 0.
const ZEROS: Self;
/// Element of the integer type with every bit as 1.
const ONES: Self;
/// Minimum value of the integer type.
const MIN: Self;
/// Maximum value of the integer type.
const MAX: Self;

/// Implements functionality for `simd_add` in `crate::abstractions::simd`.
fn wrapping_add(self, rhs: Self) -> Self;
/// Implements functionality for `simd_sub` in `crate::abstractions::simd`.
fn wrapping_sub(self, rhs: Self) -> Self;
/// Implements functionality for `simd_mul` in `crate::abstractions::simd`.
fn overflowing_mul(self, rhs: Self) -> Self;
/// Implements functionality for `simd_saturating_add` in `crate::abstractions::simd`.
fn saturating_add(self, rhs: Self) -> Self;
/// Implements functionality for `simd_saturating_sub` in `crate::abstractions::simd`.
fn saturating_sub(self, rhs: Self) -> Self;
/// Implements functionality for `simd_abs_diff` in `crate::abstractions::simd`.
fn absolute_diff(self, rhs: Self) -> Self;
/// Implements functionality for `simd_abs` in `crate::abstractions::simd`.
fn absolute_val(self) -> Self;
}

macro_rules! generate_imachine_integer_impls {
($($ty:ident),*) => {
$(
impl MachineInteger for $ty {
const SIGNED: bool = true;
const ZEROS: $ty = 0;
const ONES: $ty = -1;
const MIN: $ty = $ty::MIN;
const MAX: $ty = $ty::MAX;
fn bits() -> u32 { $ty::BITS }
fn wrapping_add(self, rhs: Self) -> Self { self.wrapping_add(rhs) }
fn wrapping_sub(self, rhs: Self) -> Self { self.wrapping_sub(rhs) }
fn overflowing_mul(self, rhs: Self) -> Self { self.overflowing_mul(rhs).0 }
fn saturating_add(self, rhs: Self) -> Self { self.saturating_add(rhs)}
fn saturating_sub(self, rhs: Self) -> Self { self.saturating_sub(rhs) }
fn absolute_diff(self, rhs: Self) -> Self {if self > rhs {$ty::wrapping_sub(self, rhs)} else {$ty::wrapping_sub(rhs, self)}}
fn absolute_val(self) -> Self {if self == $ty::MIN {self} else {self.abs()}}
})*
};
}

macro_rules! generate_umachine_integer_impls {
($($ty:ident),*) => {
$(
impl MachineInteger for $ty {
const SIGNED: bool = false;
const ZEROS: $ty = 0;
const ONES: $ty = $ty::MAX;
const MIN: $ty = $ty::MIN;
const MAX: $ty = $ty::MAX;


fn bits() -> u32 { $ty::BITS }
fn wrapping_add(self, rhs: Self) -> Self { self.wrapping_add(rhs) }
fn wrapping_sub(self, rhs: Self) -> Self { self.wrapping_sub(rhs) }
fn overflowing_mul(self, rhs: Self) -> Self { self.overflowing_mul(rhs).0 }
fn saturating_add(self, rhs: Self) -> Self { self.saturating_add(rhs)}
fn saturating_sub(self, rhs: Self) -> Self { self.saturating_sub(rhs)}
fn absolute_diff(self, rhs: Self) -> Self {if self > rhs {self - rhs} else {rhs - self}}
fn absolute_val(self) -> Self {self}
})*
};
}
generate_imachine_integer_impls!(i8, i16, i32, i64, i128);
generate_umachine_integer_impls!(u8, u16, u32, u64, u128);

impl Bit {
fn of_raw_int(x: u128, nth: u32) -> Self {
if x / 2u128.pow(nth) % 2 == 1 {
Self::One
} else {
Self::Zero
}
}

pub fn of_int<T: Into<i128> + MachineInteger>(x: T, nth: u32) -> Bit {
let x: i128 = x.into();
if x >= 0 {
Self::of_raw_int(x as u128, nth)
} else {
Self::of_raw_int((2i128.pow(T::bits()) + x) as u128, nth)
}
}
}
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